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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: WvEbwDSany0ojD/fG/FuZZtcq61fm+ZuwmyAbyeGzIpIhD2//CZl5BHkHO5fEDipJgtL3/lMo6fUwzK2h1+kCAGhOVZoGenaCoNXzwp69uUYozwtXlq1v41N+yHQWlR9ozWBGBBd3uI47u4UlFXkr8U0LfDFmXP6jPxYBgL0baoYEdu6EY+4MMviEeRuFemlurbisUIS8CFxUvZxrizCx9Bq2zInd/HqSRCU0aqcHK8FvAxQ1cz+3nJkt1zptdTv15cEEaBlgL8fgYwvSlhNFj3TlghacYMBwn/C3lGAdGIa7rCpBzpHAvvHcAv0a1HhSWj2fnx8G7lP0iQyQy6w1pHc96IFaiBUTaQMhKyoXc945gLn++M5+/DeOpBGWCJxhdbRP2t1WNySsLqATBM/hVUQRQvO/RE+sdYBxpEb+Vk= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 29d42f5c-6060-4421-4426-08d6c6ff5b4b X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2019 08:48:56.8271 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6269 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/22/2019 9:46 AM, Anson Huang wrote:=0A= >> -----Original Message-----=0A= >> From: Anson Huang=0A= >>> From: Shawn Guo [mailto:shawnguo@kernel.org]=0A= >>> On Sun, Apr 21, 2019 at 03:40:00PM +0800, Shawn Guo wrote:=0A= >>>> On Thu, Apr 11, 2019 at 06:49:12AM +0000, Anson Huang wrote:=0A= >>>>> i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller=0A= >>>>> inside, the system controller is in charge of controlling power,=0A= >>>>> clock and fuse etc..=0A= >>>>>=0A= >>>>> This patch adds i.MX system controller soc driver support, Linux=0A= >>>>> kernel has to communicate with system controller via MU (message=0A= >>>>> unit) IPC to get soc revision, uid etc..=0A= >>>>>=0A= >>>>> With this patch, soc info can be read from sysfs:=0A= >>>>>=0A= >>>>> drivers/soc/imx/Kconfig | 7 ++=0A= >>>>> drivers/soc/imx/Makefile | 1 +=0A= >>>>> drivers/soc/imx/soc-imx-sc.c | 220=0A= >>>>> +++++++++++++++++++++++++++++++++++++++++++=0A= >>>>> 3 files changed, 228 insertions(+) create mode 100644=0A= >>>>> drivers/soc/imx/soc-imx-sc.c=0A= >>>>=0A= >>>> Rather than creating a new driver, please take a look at Abel's=0A= >>>> generic=0A= >>>> i.MX8 SoC driver, and see if it can be extended to cover i.MX8QXP.=0A= >>=0A= >> Got it, I didn't notice that this patch bas been accepted, I will redo t= he patch=0A= >> based on it, thanks.=0A= > =0A= > I have sent the new patch set to support i.MX8QXP SoC revision based on g= eneric i.MX8=0A= > SoC driver, however, the Kconfig modification is NOT good, it may break i= .MX8MQ if IMX_SCU=0A= > is NOT enabled, although we can add some warp function for SCU firmware A= PI call to fix it,=0A= > but after further thought and discussion with Dong Aisheng, I think we ma= y need to roll back to=0A= > use this patch series to create a new SoC driver dedicated for i.MX8 SoCs= =0A= > with system controller inside, such as i.MX8QXP, i.MX8QM etc., the reason= are as below:=0A= > =0A= > For i.MX8MQ/i.MX8MM:=0A= > 1. SoC driver does NOT depends on i.MX SCU firmware, so no need to use p= latform driver=0A= > probe model, just device_init phase call is good enough;=0A= > 2. The SoC driver no need to depends on IMX_SCU, so it can be always bui= lt in, no need to=0A= > check IMX_SCU config;=0A= > 3. The fuse check for CPU speed grading, HDCP status, NoC settings etc. = could be added to this driver,=0A= > but they are ONLY for i.MX8MQ/i.MX8MM etc..=0A= > For i.MX8QXP/i.MX8QM:=0A= > 1. SoC driver MUST depends on IMX_SCU;=0A= > 2. MUST use platform model to support defer probe;=0A= > 3. No fuse check for CPU speed grading.=0A= > =0A= > So, I guess the reused code for i.MX8MQ and i.MX8QXP is ONLY those part o= f creating SoC id device node (less than=0A= > 30% I think), all other functions are implemented in total different ways= , that is why I created the imx_sc_soc driver=0A= > in this patch series, so do you think we can add new SoC driver for i.MX8= SoC with SCU inside? Putting 2 different architecture=0A= > SoCs' driver into 1 file looks like NOT making enough sense.=0A= =0A= +1 for separate SOC driver. The 8mq/8mm and 8qm/8qxp families are very =0A= different, they just happen to share the imx8 prefix.=0A= =0A= It makes sense to allow people to compile one without the other and this = =0A= is easier with distinct SOC drivers.=0A= =0A= --=0A= Regards,=0A= Leonard=0A=