Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp3222171yba; Mon, 22 Apr 2019 23:12:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqwfuOvkz7T+8u4YPT+1Ha/zn3VdEJBMf7SYDQv8uBifsRMkRwnDBg/hgjMDOiX+o/IZ0T6y X-Received: by 2002:a65:6088:: with SMTP id t8mr23089248pgu.2.1555999956816; Mon, 22 Apr 2019 23:12:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555999956; cv=none; d=google.com; s=arc-20160816; b=0AegHp5k8xh/XXByIldcExIdJFQBGL0NMabiPCCAqC0XCNZjJ8Wk4uxE5jpCEGKial /V3bYrkDr1XWpcPkY6Sf2eu6BHkkYHY1/QulPIjH09MfG/YW9qNtblvDwJp8mDHl7QDS 5v++nQO8LbTOQy1+NAc7MJJcIVhF+Y0JgTjOj7Qd/GUM+QdMCK9jYDwWIv4wdC9jIuOR 8p5l4TxQX1qIh2OK3+o+uQNFC8hs7rEfSDy1Loxc2SqNNDE5RDCOk9xhGSYb0S8O58mU U0xh85Y9AeFDh0mXVZLululq9wkBoUPxz5cIdbpLRWbGXnhZcdqKrN3UodaACPfS/0Nt hYMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=DXlOvuZYSdUB+yHdA5IR4gKX5pBtQSwNt7fKtc0Xups=; b=yrubYgMDzBR8krqBRCmYOHjygLl+gXAnp746Qy7Y5eRNLv3UtfZuJUk+MDEyjMxSGy vJb47/KmWEfcjQdQLIKQTv7oqU6NRbTtBrfGtWNHiWaCXwbsSLpbKbSmxJexeFwWisDb rb2U40yDBkApALBWNtUrSp7bkiI8D8N83vGvHVKpg8j9wZb6o/SP4sGDT8r5G5XcZFjP Om/gWQdUZaiPqNcd1kjMayZ6+FyTeSL2tJIf5l7XaE5fk/zyeToKviaIOmlZQFNOcojA kUTikwoTnQCe+pZBODqe1L+KyUSnlh5ZfbbcgplyRgMRJJTRlRhq2GxSOF9/e91hgJHo 3mpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=pdy2y4kb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 127si16304499pfz.28.2019.04.22.23.12.21; Mon, 22 Apr 2019 23:12:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=pdy2y4kb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726057AbfDWGL3 (ORCPT + 99 others); Tue, 23 Apr 2019 02:11:29 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:15200 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725882AbfDWGL3 (ORCPT ); Tue, 23 Apr 2019 02:11:29 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 22 Apr 2019 23:11:33 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 22 Apr 2019 23:11:27 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 22 Apr 2019 23:11:27 -0700 Received: from [10.25.75.193] (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr 2019 06:11:21 +0000 Subject: Re: [PATCH V3 04/16] PCI: dwc: Perform dbi regs write lock towards the end To: Jisheng Zhang , Gustavo Pimentel , Hou Zhiqiang CC: "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "thierry.reding@gmail.com" , "jonathanh@nvidia.com" , "kishon@ti.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "lorenzo.pieralisi@arm.com" , "jingoohan1@gmail.com" , "devicetree@vger.kernel.org" , "mmaddireddy@nvidia.com" , "kthota@nvidia.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "mperttunen@nvidia.com" , "linux-tegra@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "sagar.tv@gmail.com" References: <20190416192730.15681-1-vidyas@nvidia.com> <20190416192730.15681-5-vidyas@nvidia.com> <305100E33629484CBB767107E4246BBB0A22C127@de02wembxa.internal.synopsys.com> <20190422154608.6e6f8ae3@xhacker.debian> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Tue, 23 Apr 2019 11:41:18 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190422154608.6e6f8ae3@xhacker.debian> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL104.nvidia.com (172.18.146.11) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555999893; bh=DXlOvuZYSdUB+yHdA5IR4gKX5pBtQSwNt7fKtc0Xups=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=pdy2y4kbl2u46CjtnSmDv3q9OwtcfmZ6aH1MdXfIPuA6AzWXhc6KE3cy0R426sN23 K8x8OOsPwF6RRxOgSMLveqGfLEfD1T9IdKP/zIxPSUK8tEhs8YdYhLay3bEtwByvNR Yb/EJuQuIM6LBQwYNhEOTq0CPJ54vAb6eVrolFd6+fodnZGC1oTwIs79OPyHhjqhWV fL3qGpgWpxhspS/DTiDtuTTmB2Bf1ub1z4mfMa45vPfow/y0FYeTiqrOKjI7sh1Nh/ lwQH0fUPA/T1GsSEnKdm6ka3brJ8gDyq2ShYW+IX1UKK7qdNTfIm4Ixx7b3200jpBD mXHHEb5ndo0Bw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/22/2019 1:24 PM, Jisheng Zhang wrote: > On Wed, 17 Apr 2019 09:56:33 +0000 Gustavo Pimentel wrote: > >> >> On Tue, Apr 16, 2019 at 20:27:18, Vidya Sagar wrote: >> >>> Remove multiple write enable and disable sequences of dbi registers as >>> Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by >>> DBI write-lock enable bit thereby not allowing any further writes to BAR-0 >>> register in config space to take place. Hence disabling write permission >>> only towards the end. >>> >>> Signed-off-by: Vidya Sagar >>> --- >>> Changes since [v2]: >>> * None >>> >>> Changes since [v1]: >>> * None >>> >>> drivers/pci/controller/dwc/pcie-designware-host.c | 3 --- >>> 1 file changed, 3 deletions(-) >>> >>> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >>> index 2a5332e5ccfa..c0334c92c1a6 100644 >>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >>> @@ -683,7 +683,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) >>> val &= 0xffff00ff; >>> val |= 0x00000100; >>> dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); >>> - dw_pcie_dbi_ro_wr_dis(pci); >>> >>> /* Setup bus numbers */ >>> val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); >>> @@ -723,8 +722,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) >>> >>> dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); >>> >>> - /* Enable write permission for the DBI read-only register */ >>> - dw_pcie_dbi_ro_wr_en(pci); >>> /* Program correct class for RC */ >>> dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); >>> /* Better disable write permission right after the update */ >>> -- >>> 2.17.1 >> >> This setup sequence was written by Jingoo Han, let's check if he did this >> by some particular reason. >> Jingoo do you remember why you wrote the code like this? > > FWICT, enabling RO writeable in the setup sequence is introduced in > commit d91dfe5054d4 ("PCI: dwc: Enable write permission for Class Code, > Interrupt Pin updates"). The Reason why not towards the end maybe > only enable the RO writeable when necessary. In that case, my patch shouldn't cause any issue and if any it would avoid few writes to speed up the process. So, in my opinion, it is a good to go change. Please let me know if you have disagree with me on this. > > thanks >