Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp3320752yba;
        Tue, 23 Apr 2019 01:30:09 -0700 (PDT)
X-Google-Smtp-Source: APXvYqymJhRKpra1gUHWqXMt2uCLo3HN84mnynqDlzp5AEBil8Ess/H2D810zKHn7zCCIVSa2s2E
X-Received: by 2002:a62:6f47:: with SMTP id k68mr25616729pfc.196.1556008208087;
        Tue, 23 Apr 2019 01:30:08 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1556008207; cv=none;
        d=google.com; s=arc-20160816;
        b=n67qtJRG9W5US1uoc7nX5lIV3xdCAhtBVtUqDz3DcU++HbH1SF8H6eNzQeL3TU8QNj
         X7KtuOusMisK9z9n+kmALVSjI5xki3rP9kPpv0n/pHAl/ClRF0HCE7ADvXKWb9UgbRp4
         UEkuVIK20ofzHEqKR5QyoyfWChLu7aQMFK0rP7WQIP8u1P8jza/Gu407qVHB4EonsEf9
         KeuyrpMKFhaQfv+9ema4sNyMEYGjmfCsVq94lMXhDW0BygRJNk6He7Rq5T9y9YzCInKo
         FCzNTssLOamvlSX41/v6v3/uO9Rzoiv4cTxm/FVibExRyBIExMVrbu80JfA2OvvRspNO
         vY6g==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:dkim-signature:mime-version:references
         :in-reply-to:message-id:date:subject:cc:to:from;
        bh=GKdi95t5IVrmlblKc5/Uv+CvvQtd8a50ZpNkbBcFscM=;
        b=J63MSKQxi6JoDii+PMFQ2ue2AOIXuWx8+oNF4lTdqdaokQnk0vu88567mAv/EO1L1h
         EWEWseF1VoXohcSA0pTbHBPBXBSa/8CFDHU88vMle32DY2XcYLkcDkGnIlCxa/s3ITye
         aWhTaMZsFDpzb2GORUwAgxRsQXlhL9LbceIAzcwXjlUOJo4hlrJfpi5KHQLaOtAsfZ6D
         ZtmwtpBalTY6mNCAGq3M+5vW0kuFLcNaPXH3MYWBE6P1hFwsNtj5by2FZ6//KypA+zBL
         n8PBj8CAJLisEECVKVhslsHGfNq7JCT6ou4fMCQGijfRxa/RPQhFTBZe2aVwwxRquKWM
         tYAQ==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=ABZj8Q6W;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id x15si1385801pln.135.2019.04.23.01.29.52;
        Tue, 23 Apr 2019 01:30:07 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=ABZj8Q6W;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1726928AbfDWI2Q (ORCPT <rfc822;mailist1go@gmail.com>
        + 99 others); Tue, 23 Apr 2019 04:28:16 -0400
Received: from hqemgate16.nvidia.com ([216.228.121.65]:2650 "EHLO
        hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1726821AbfDWI2O (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Tue, 23 Apr 2019 04:28:14 -0400
Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5cbecc9a0002>; Tue, 23 Apr 2019 01:28:10 -0700
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate102.nvidia.com (PGP Universal service);
  Tue, 23 Apr 2019 01:28:14 -0700
X-PGP-Universal: processed;
        by hqpgpgate102.nvidia.com on Tue, 23 Apr 2019 01:28:14 -0700
Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL106.nvidia.com
 (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr
 2019 08:28:13 +0000
Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL112.nvidia.com
 (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 23 Apr
 2019 08:28:13 +0000
Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com
 (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend
 Transport; Tue, 23 Apr 2019 08:28:13 +0000
Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5cbecc980003>; Tue, 23 Apr 2019 01:28:13 -0700
From:   Vidya Sagar <vidyas@nvidia.com>
To:     <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
        <robh+dt@kernel.org>, <mark.rutland@arm.com>,
        <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
        <kishon@ti.com>, <catalin.marinas@arm.com>, <will.deacon@arm.com>,
        <jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>
CC:     <mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
        <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V4 05/16] PCI: dwc: Move config space capability search API
Date:   Tue, 23 Apr 2019 13:57:19 +0530
Message-ID: <20190423082730.370-6-vidyas@nvidia.com>
X-Mailer: git-send-email 2.17.1
In-Reply-To: <20190423082730.370-1-vidyas@nvidia.com>
References: <20190423082730.370-1-vidyas@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1556008091; bh=GKdi95t5IVrmlblKc5/Uv+CvvQtd8a50ZpNkbBcFscM=;
        h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
         In-Reply-To:References:X-NVConfidentiality:MIME-Version:
         Content-Type;
        b=ABZj8Q6WOZHJDR9YG0tMx3mGq1LnCxo0PWI3Os1neISrfN9yk7G+8x0b2nZV11gtE
         G+mklMly8yzJvHkr8F+QjG8FLG+FsTVW8uMC85AliUNZ4cI6jZChhhQTme1lmTyDg+
         fD3F7qAW5EfFarlWHwdZlfo0lzUUJ0TwljqB9Ng/ZTA8ObIy/S51oa1ANT4Pnl7G7C
         QIKXaMlkTdDdwDiYxGCPWwzcE/IhCpDqVAPwsPv4gVW6i16v9NV97JeL7YHKfLK3zW
         dUkQpBZCr2YU/Tf2sdpjILl2q8aVxmwJ3FoERn96CJZ+HJjeuWa7JWTe8IOxduiFvJ
         BSl89jv2PdykA==
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and ep mode codes.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Changes from [v3]:
* Rebased to linux-next top of the tree

Changes from [v2]:
* None

Changes from [v1]:
* Removed dw_pcie_find_next_ext_capability() API from here and made a
  separate patch for that

 drivers/pci/controller/dwc/pcie-designware.c | 33 ++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h |  2 ++
 2 files changed, 35 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 8e0081ccf83b..6a98135244d6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -20,6 +20,39 @@
 #define PCIE_PHY_DEBUG_R1_LINK_UP	(0x1 << 4)
 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING	(0x1 << 29)
 
+static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
+				  u8 cap)
+{
+	u8 cap_id, next_cap_ptr;
+	u16 reg;
+
+	reg = dw_pcie_readw_dbi(pci, cap_ptr);
+	next_cap_ptr = (reg & 0xff00) >> 8;
+	cap_id = (reg & 0x00ff);
+
+	if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
+		return 0;
+
+	if (cap_id == cap)
+		return cap_ptr;
+
+	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+}
+
+u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
+{
+	u8 next_cap_ptr;
+	u16 reg;
+
+	reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
+	next_cap_ptr = (reg & 0x00ff);
+
+	if (!next_cap_ptr)
+		return 0;
+
+	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+}
+
 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
 {
 	if (!IS_ALIGNED((uintptr_t)addr, size)) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 9ee98ced1ef6..35160b4ce929 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -248,6 +248,8 @@ struct dw_pcie {
 #define to_dw_pcie_from_ep(endpoint)   \
 		container_of((endpoint), struct dw_pcie, ep)
 
+u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
+
 int dw_pcie_read(void __iomem *addr, int size, u32 *val);
 int dw_pcie_write(void __iomem *addr, int size, u32 val);
 
-- 
2.17.1