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a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1556008102; bh=Xyuc4umDDsNoUYu4A3yS3VHFlPa+cbHBrCTOkJl4jTI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=jlXA5RWg0dVtPpZ6xMk9J3tvl2eJQAsylhqBcPlQrppSgkjslW8CJj7xc/CXJOtdx Z0TI4mEZBPnTjaB2nsHnChb9vSBEcFVWymZb/t9C29h6uh1HVynC+nLBnjINr1fUax 9qIGPuQyVjmckyctzqpvBWkCbrhbMS0K14dF1Kgh3DIBDkWR4WBs72iIBzZChE0Hx+ 42n56ReD67+sxp2mg4jUkIyF67u+h3Qm29f2/FrJyPW0y4hBK/lbY/a4NkQDILOrnX kVqhYqsauEYXCI8r2kjt1M/cWObx+Xh3gbQtEUhbSygQMPV+31ikr8xRaLUP6EGtmn RzJMZpbqVo2wA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add extended configuration space capability search API using struct dw_pcie * pointer Signed-off-by: Vidya Sagar Acked-by: Gustavo Pimentel --- Changes from [v3]: * None Changes from [v2]: * None Changes from [v1]: * This is a new patch in v2 series drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 42 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6a98135244d6..ecf5fe8842f6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); } +static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start, + int cap) +{ + u32 header; + int ttl; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (start) + pos = start; + + header = dw_pcie_readl_dbi(pci, pos); + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap && pos != start) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + header = dw_pcie_readl_dbi(pci, pos); + } + + return 0; +} + +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap) +{ + return dw_pcie_find_next_ext_capability(pci, 0, cap); +} +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 35160b4ce929..67307842e003 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -249,6 +249,7 @@ struct dw_pcie { container_of((endpoint), struct dw_pcie, ep) u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); -- 2.17.1