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From:   Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>
To:     Jisheng Zhang <Jisheng.Zhang@synaptics.com>,
        Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>,
        Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
CC:     Vidya Sagar <vidyas@nvidia.com>,
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        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "mark.rutland@arm.com" <mark.rutland@arm.com>,
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Subject: RE: [PATCH V3 04/16] PCI: dwc: Perform dbi regs write lock towards
 the end
Thread-Topic: [PATCH V3 04/16] PCI: dwc: Perform dbi regs write lock towards
 the end
Thread-Index: AQHU9IqKd2QC8WkfMUGD8rhulPpCxqZAHDUQgAeabACAAc8x0A==
Date:   Tue, 23 Apr 2019 09:40:40 +0000
Message-ID: <305100E33629484CBB767107E4246BBB0A22FA36@de02wembxa.internal.synopsys.com>
References: <20190416192730.15681-1-vidyas@nvidia.com>
        <20190416192730.15681-5-vidyas@nvidia.com>
        <305100E33629484CBB767107E4246BBB0A22C127@de02wembxa.internal.synopsys.com>
 <20190422154608.6e6f8ae3@xhacker.debian>
In-Reply-To: <20190422154608.6e6f8ae3@xhacker.debian>
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On Mon, Apr 22, 2019 at 8:54:32, Jisheng Zhang=20
<Jisheng.Zhang@synaptics.com> wrote:

> On Wed, 17 Apr 2019 09:56:33 +0000 Gustavo Pimentel wrote:
>=20
> >=20
> > On Tue, Apr 16, 2019 at 20:27:18, Vidya Sagar <vidyas@nvidia.com> wrote=
:
> >=20
> > > Remove multiple write enable and disable sequences of dbi registers a=
s
> > > Tegra194 implements writes to BAR-0 register (offset: 0x10) controlle=
d by
> > > DBI write-lock enable bit thereby not allowing any further writes to =
BAR-0
> > > register in config space to take place. Hence disabling write permiss=
ion
> > > only towards the end.
> > >
> > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> > > ---
> > > Changes since [v2]:
> > > * None
> > >
> > > Changes since [v1]:
> > > * None
> > >
> > >  drivers/pci/controller/dwc/pcie-designware-host.c | 3 ---
> > >  1 file changed, 3 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/driv=
ers/pci/controller/dwc/pcie-designware-host.c
> > > index 2a5332e5ccfa..c0334c92c1a6 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > @@ -683,7 +683,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> > >       val &=3D 0xffff00ff;
> > >       val |=3D 0x00000100;
> > >       dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
> > > -     dw_pcie_dbi_ro_wr_dis(pci);
> > >
> > >       /* Setup bus numbers */
> > >       val =3D dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
> > > @@ -723,8 +722,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> > >
> > >       dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
> > >
> > > -     /* Enable write permission for the DBI read-only register */
> > > -     dw_pcie_dbi_ro_wr_en(pci);
> > >       /* Program correct class for RC */
> > >       dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_P=
CI);
> > >       /* Better disable write permission right after the update */
> > > --
> > > 2.17.1 =20
> >=20
> > This setup sequence was written by Jingoo Han, let's check if he did th=
is
> > by some particular reason.
> > Jingoo do you remember why you wrote the code like this?
>=20
> FWICT, enabling RO writeable in the setup sequence is introduced in
> commit d91dfe5054d4 ("PCI: dwc: Enable write permission for Class Code,=20
> Interrupt Pin updates"). The Reason why not towards the end maybe
> only enable the RO writeable when necessary.

I also share that belief, in any case, I just want to confirm with the=20
original developer if this was coded like this for some good reason,=20
maybe to force some additional protection. Otherwise, I think the=20
presented patch is harmless.

Gustavo

>=20
> thanks