Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp3434663yba; Tue, 23 Apr 2019 03:53:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqysyHKNU5B37SUKkbIh+qUJUpR7OZNgYEw7JPgOwtIKK9FatFQoLfqkE7VQN85GCKpSriCp X-Received: by 2002:aa7:8019:: with SMTP id j25mr26490420pfi.77.1556016792495; Tue, 23 Apr 2019 03:53:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556016792; cv=none; d=google.com; s=arc-20160816; b=rgDb7iQZOQ02iwrm0aQCaMQsV0kYF5FKvs5EMInCroH/GzLNm8Ibe/cqZt87zgbPi1 usGD4fOx0WQvtuRQp1b5q7cMuq+c6GItmopWFOWj91DmZTKJM/aIz8a2ziIxVl/XpkkN sTgMeaqck+Yjphd3Tl9Jt8GAm1vjxvMW/ZqMVNK2X0ht9SdGb7c9ZrG9yWJiO2Xwg0g0 IJjA0TLj9p/ySHQ+EZiQ9T61s7H/lSBsUYIkysqGdDjXUf5+vxUomD+hpnvbV/ARQXtM 7RFmkgmttPFHODfwcgKkIjYVXumaMNTLaoDl1V7GdVcgP6TXt7ZPr7fTq/F/GZVx07YF ZZOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:organisation:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=nkIgPJxyqyvHFG6CUcYVAmo224/9fscEQPnlg98Sn3k=; b=lN+Ebj8rsXg+YDbQjNkv4vYUzQtrvX16S2yYvCpVtyBVAQTIL8n3psV7aR5iDasmC/ uEbk+AB1MmDCz69a0Vwnjx+VlmVeWfOqvDCbbu1i7rJHSKirJo03R7atB5oWfaklAqH3 s+bDlDXsDsalVPsmbFpZmo4YqpJUipNcBYFCmCj643VC4780dJDgQhT3qBVOaddX2h8W xk0JT6XBC9V3bPhWMcz/ihj1v0rM/Nvp4BhZAaz8KKC97QmW96ZVRqXVcBmlATf6J4rR 9BGwK3eSpqmlbqg8TEdO+sGgLzVcnf2Qnfpmdg/FZKGHTjzYw4nIhyYbURhPXgI4JhSc 6B0Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j5si15742577pfa.63.2019.04.23.03.52.57; Tue, 23 Apr 2019 03:53:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727501AbfDWKuv (ORCPT + 99 others); Tue, 23 Apr 2019 06:50:51 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:46930 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725990AbfDWKuu (ORCPT ); Tue, 23 Apr 2019 06:50:50 -0400 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id B8A5025AE8B; Tue, 23 Apr 2019 20:50:48 +1000 (AEST) Received: by reginn.horms.nl (Postfix, from userid 7100) id AD3469403E4; Tue, 23 Apr 2019 12:50:46 +0200 (CEST) Date: Tue, 23 Apr 2019 12:50:46 +0200 From: Simon Horman To: Nguyen An Hoan Cc: linux-renesas-soc@vger.kernel.org, ramesh.shanmugasundaram@bp.renesas.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kuninori.morimoto.gx@renesas.com, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, h-inayoshi@jinso.co.jp, cv-dong@jinso.co.jp Subject: Re: [PATCH 1/2] media: dt-bindings: media: Add r8a77965 DRIF bindings Message-ID: <20190423105046.cshmwghdufaqp4pj@verge.net.au> References: <1556014199-12698-1-git-send-email-na-hoan@jinso.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1556014199-12698-1-git-send-email-na-hoan@jinso.co.jp> Organisation: Horms Solutions BV User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 23, 2019 at 07:09:58PM +0900, Nguyen An Hoan wrote: > From: Hoan Nguyen An > > Add r8a77965 DRIF bindings. > > Signed-off-by: Hoan Nguyen An According to the User's Manual Hardware, v1.50 Nov 20 2019, the DRIF IP block M3-N (r8a77965) has a BITCTR register which is not present on the H3 (r8a7795) or M3-W (r8a77995). Does the DRIF IP block present on the M3-N (r8a77965) function without support for this register in the driver? If not then I think that: 1) This patch should be updated to note that renesas,rcar-gen3-drif can only be used with H3 (r8a7795) and M3-W (r8a77995). 2) A driver patch is required 3) The DT patch, 2/2 of this series, should be updated to i) Not use renesas,rcar-gen3-drif ii) Extend the register aperture from 0x64 to 0x84. > --- > Documentation/devicetree/bindings/media/renesas,drif.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/media/renesas,drif.txt b/Documentation/devicetree/bindings/media/renesas,drif.txt > index 0d8974a..16cdee3 100644 > --- a/Documentation/devicetree/bindings/media/renesas,drif.txt > +++ b/Documentation/devicetree/bindings/media/renesas,drif.txt > @@ -41,6 +41,7 @@ Required properties of an internal channel: > ------------------------------------------- > - compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC. > "renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC. > + "renesas,r8a77965-drif" if DRIF controller is a part of R8A77965 SoC. > "renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device. > > When compatible with the generic version, nodes must list the > -- > 2.7.4 >