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received-spf: None (protection.outlook.com: garyguo.net does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: puKGsbHkRRB6oGuSPbECyRT356zY3Uht2uhASlVpRvR6hazKUBHKShshuQkNr0VfUwY68yWOQJnOP31AjpjIS3T/RELnuVfrqII4XX78DE6mkYYjp2Bl9m0fMhDZLd0fBWr91bR4720jsYK2VubvWoUioZn5wyGVEBCf3uie9D3ItMR9rYDhXZCZsmOoY9sSXVWTKormCttXuHSR+dwGYCs45gVlpHaOZ4E4AJ/mezjG8JIZYwOd5PpmfDmnTmLZ+WaS4ZvDdxUXxa8aa2YTu6lNpIjjvtVRE1HgYDxFcMSyLGbcWn0y3ed5Ont899Q4/MPNNBVrkaTIZY/xZzkKU+YVPPY2SHbKvF51VnuJMGd5szWm6K2RrRpIGpQup/fycz2B1Q9vjPOhHaq3qdFEysuBpRdAjBFz82jrH9VbAyQ= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: garyguo.net X-MS-Exchange-CrossTenant-Network-Message-Id: 4255b0f9-9f1e-4b17-0f35-08d6c863e8b8 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Apr 2019 03:21:15.0187 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: bbc898ad-b10f-4e10-8552-d9377b823d45 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: LO2P265MB0157 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Guo Ren > Sent: Wednesday, April 24, 2019 03:08 > To: Gary Guo > Cc: Christoph Hellwig ; linux-arch@vger.kernel.org; Palmer > Dabbelt ; Andrew Waterman ; Arnd > Bergmann ; Anup Patel ; Xiang > Xiaoyan ; linux-kernel@vger.kernel.org; Mike > Rapoport ; Vincent Chen ; > Greentime Hu ; ren_guo@c-sky.com; linux- > riscv@lists.infradead.org; Marek Szyprowski ; > Robin Murphy ; Scott Wood ; > tech-privileged@lists.riscv.org > Subject: Re: [PATCH] riscv: Support non-coherency memory model >=20 > Hi Gary, >=20 > On Tue, Apr 23, 2019 at 03:57:30PM +0000, Gary Guo wrote: > > >>> Another point is we could get more attribute bits by modify the ris= cv > > >>> spec: > > >>> - Remove Global bit, I think it's duplicate with the User bit in = linux. > > >> > > >> It is in Linux, but it is conceptually very different. > > > Yes, but hardware could ignore one of them and in riscv linux > > > _PAGE_GLOBAL is no use at all, see: > > > grep _PAGE_GLOBAL arch/riscv -r > > > > > > In fact, the _PAGE_KERNEL for pte doesn't contain _PAGE_GLOBAL and it > > > works on FU540 and qemu. As I've mentioned page attribute bits is ver= y > > > precious, define a useless bit make people confused. > > > > > > > The fact that it isn't used yet doesn't imply it is not useful. We don'= t > > use ASIDs at the moment, and without using ASIDs the "global" bit is > > indeed not useful. However with ASIDs the bit will be vital for saving > > TLB spaces. Without the global bit, the kernel pages become synonyms to > > themselves (i.e. they have different tags in TLB but refer to the same > > physical page). > > > > The global bit also exists in many other ISAs as well. It's definitely > > not a "useless" bits. > > > > Moreover, this bit is already implemented in both Rocket and Ariane. It > > is also in the spec for quite a while. The fact that Linux doesn't use > > it at the moment is not a reason for removing it. > > >=20 > Look: > linux-next git:(riscv_asid_allocator_v2)$ grep GLOBAL arch/riscv -r > arch/riscv/include/asm/pgtable-bits.h:#define _PAGE_GLOBAL (1 << 5) = /* > Global */ > arch/riscv/include/asm/pgtable-bits.h: = _PAGE_USER | > _PAGE_GLOBAL)) >=20 > Your patch tell us _PAGE_USER and _PAGE_GLOBAL are duplicate and why we > couldn't make _PAGE_USER implies _PAGE_GLOBAL? Can you give an example > of a real scene in PTE about: > _PAGE_USER:0 + _PAGE_GLOBAL:1 > or > _PAGE_USER:1 + _PAGE_GLOBAL:0 >=20 > Of cause I know USER & GLOBAL are conceptually very different, but > there are only 10 attribute-bits for riscv (In fact we've wasted two bits > to support huge RV32-pfn :P). So I think it is time to merge these two bi= ts > before hardware supports GLOBAL. Reserve them for future! Two cases I can think of: * vdso like things. They're user pages that can really be shared across add= ress spaces (i.e. global). Kernels like L4 implement most systems calls sim= ilar to VDSO, so USER + GLOBAL is useful. * hypervisor without H-extension: This requires shadow page tables. Supervi= sor pages are mapped to supervisor shadow pages. However these shadow pages= cannot be GLOBAL because they can't be shared between VMs. So !USER + !GL= OBAL is useful. Remember Linux isn't the only supervisor software that RISC-V cares!=20 >=20 > Best Regards > Guo Ren