Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Matt Redfearn <matt.redfearn@thinci.com>
To:     Andrzej Hajda <a.hajda@samsung.com>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Philippe Cornu <philippe.cornu@st.com>
CC:     "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
        Matthew Redfearn <matthew.redfearn@thinci.com>,
        Nickey Yang <nickey.yang@rock-chips.com>,
        Heiko Stuebner <heiko@sntech.de>,
        Archit Taneja <architt@codeaurora.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>
Subject: [PATCH] drm/bridge/synopsys: dsi: Wait for all active lanes to reach
 stop
Thread-Topic: [PATCH] drm/bridge/synopsys: dsi: Wait for all active lanes to
 reach stop
Thread-Index: AQHU+qkIdYdzVBhVUEOlClcEU/eg/w==
Date:   Wed, 24 Apr 2019 14:21:40 +0000
Message-ID: <20190424142124.25776-1-matt.redfearn@thinci.com>
Accept-Language: en-GB, en-US
Content-Language: en-US
x-ms-exchange-messagesentrepresentingtype: 1
x-mailer: git-send-email 2.17.1
x-originating-ip: [87.242.198.86]
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: 820878b5-bf5f-426d-8f70-08d6c8c02b17
x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600141)(711020)(4605104)(2017052603328)(7193020);SRVR:MA1PR01MB3194;
x-ms-traffictypediagnostic: MA1PR01MB3194:
x-microsoft-antispam-prvs: <MA1PR01MB319466076B2EE9453B138B66F13C0@MA1PR01MB3194.INDPRD01.PROD.OUTLOOK.COM>
x-forefront-prvs: 00179089FD
x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(136003)(39850400004)(396003)(376002)(366004)(346002)(189003)(199004)(8676002)(316002)(2906002)(2616005)(486006)(476003)(66066001)(36756003)(81166006)(14454004)(81156014)(478600001)(6506007)(256004)(14444005)(386003)(26005)(68736007)(186003)(66946007)(73956011)(5660300002)(64756008)(66476007)(3846002)(6116002)(66556008)(50226002)(7416002)(66446008)(8936002)(102836004)(6512007)(71190400001)(1076003)(71200400001)(52116002)(97736004)(53936002)(4326008)(6436002)(25786009)(7736002)(305945005)(99286004)(6486002)(110136005)(54906003);DIR:OUT;SFP:1102;SCL:1;SRVR:MA1PR01MB3194;H:MA1PR01MB3770.INDPRD01.PROD.OUTLOOK.COM;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1;
received-spf: None (protection.outlook.com: thinci.com does not designate
 permitted sender hosts)
x-ms-exchange-senderadcheck: 1
x-microsoft-antispam-message-info: P9/Z/7BlToXBmSSyaGlMKpoMexfsTEeGzN3mmlVkdzjZwQse3JedpISC/xkKTbCj3djho2xzgTuehokrBg6scn5RWMaZojfbchH1cwcd39RMamyoSzt1s88cwQrWCbUEGxpSdbpbzLoaFSpYyDqFy857nxmv+lyW44N33LGoJdXbx5X/zV4ahGssEzJuIO9Ya3mPlK2Iwwdw9ntmX7WyhJyhvBXJep2vOobcT4AO2mRRxd5x66N0FXXI3bVtMn7pc3OQnul61km16TmhwK6D5Gy7/k29iV1ibzPrE3lFwriYrGJlPmHc/pmitjfJt2BKCJR21rY0mGNhpNphEKcIVEo4D3wR+CAuj1LCDRYoB0kl+ItTLOtspMP1IVb5eAcQfPHcaQyx+Dv0pV+ncjDi5jmh25nEWIjheF0bWvGMZE4=
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: thinci.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 820878b5-bf5f-426d-8f70-08d6c8c02b17
X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Apr 2019 14:21:40.3535
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 9d1c3c89-8615-4064-88a7-bb1a8537c779
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MA1PR01MB3194
X-TMASE-Version: StarCloud-1.3-8.2.1013-24572.000
X-TMASE-Result: 10--0.878200-4.000000
X-TMASE-MatchedRID: zgaLmhMzJJS+YICiYwDgGRz2MDiYujy5kKAa/khZ3iT7efdnqtsaEx9Y
        5WQrOqCXo5qw/iFKtvYBtjkcfRMmqe3NIrNSYNRXS3OTftLNfg36Vf9FxCgbYTb9TB28Ubki+lM
        TBggE22Hi8zVgXoAlttUfIakorPe9T6cNbCp0hFxqHXONfTwSQsRB0bsfrpPIcSqbxBgG0w7IRb
        WdBCMsjs4DJ3/ByS2DxxoQfEOw/34l5kC9tkv6slsiQ4mr4segZd0iQ4jvVcJYZuXuhxBJBzDh0
        5MOYuzrPK+rRaMT815cO9B/xExylnaERdAplYSnCe1QEhIfRoDrAQ1iKyyQ4g==
X-TM-Deliver-Signature: 42E5E377544E3B789E728AC624520790
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

The Synopsys manual states that software should wait for all active
lanes to reach stop state (User manual section 3.1.5). Currently the
driver only waits for / checks that the clock lane is in stop state. Fix
this by waiting for the mask of PHY STATUS bits corresponding to the
active lanes to be set.

Signed-off-by: Matt Redfearn <matt.redfearn@thinci.com>

---

 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/dr=
m/bridge/synopsys/dw-mipi-dsi.c
index bd15c21a177..38e88071363 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -189,6 +189,10 @@
 #define DSI_PHY_TX_TRIGGERS		0xac
=20
 #define DSI_PHY_STATUS			0xb0
+#define PHY_STOP_STATE_LANE_3		BIT(11)
+#define PHY_STOP_STATE_LANE_2		BIT(9)
+#define PHY_STOP_STATE_LANE_1		BIT(7)
+#define PHY_STOP_STATE_LANE_0		BIT(4)
 #define PHY_STOP_STATE_CLK_LANE		BIT(2)
 #define PHY_LOCK			BIT(0)
=20
@@ -752,7 +756,7 @@ static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *d=
si)
=20
 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
 {
-	u32 val;
+	u32 val, mask;
 	int ret;
=20
 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
@@ -763,11 +767,16 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_ds=
i *dsi)
 	if (ret)
 		DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
=20
+	mask =3D PHY_STOP_STATE_CLK_LANE | PHY_STOP_STATE_LANE_0;
+	mask |=3D (dsi->lanes >=3D 2) ? PHY_STOP_STATE_LANE_1 : 0;
+	mask |=3D (dsi->lanes >=3D 3) ? PHY_STOP_STATE_LANE_2 : 0;
+	mask |=3D (dsi->lanes =3D=3D 4) ? PHY_STOP_STATE_LANE_3 : 0;
+
 	ret =3D readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
-				 val, val & PHY_STOP_STATE_CLK_LANE, 1000,
+				 val, (val & mask) =3D=3D mask, 1000,
 				 PHY_STATUS_TIMEOUT_US);
 	if (ret)
-		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
+		DRM_DEBUG_DRIVER("failed to wait phy stop state\n");
 }
=20
 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
--=20
2.17.1