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[209.132.180.67]) by mx.google.com with ESMTP id a4si5258116pgb.466.2019.04.24.07.49.37; Wed, 24 Apr 2019 07:49:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@arista.com header.s=googlenew header.b=d0x1GTdS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=arista.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731096AbfDXOr6 (ORCPT + 99 others); Wed, 24 Apr 2019 10:47:58 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:44932 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732335AbfDXOrw (ORCPT ); Wed, 24 Apr 2019 10:47:52 -0400 Received: by mail-wr1-f68.google.com with SMTP id c5so16688921wrs.11 for ; Wed, 24 Apr 2019 07:47:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arista.com; s=googlenew; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=XEa6rgZnUyAXDzw6k5Wm7RfYfnHAGNjNhYDmbAFVjBc=; b=d0x1GTdScmTi/VkiE0XNzsl/xx34iXYLR6LOxCKLsTXf+xKgooxCZ2Xyd8J8W86ncJ vKseDrctWz4KkIRGBf0ExMi26sVrdk7SnFZgrv4RRSsaVETnvp43d8M8tp/viyukTj+N MRlu6ZmZEZo1ZDzwWkG77AETW1r0ukTgnI8fDtumDz5z3Avf9SIGQPvGwh1Xd5KnGmXd jZHtvBnQjh33rlWdCP/1Z9O0+GiDh0yQHhB0gsbhD7Hv8JszATRIDEM7PBfPlxLYzKYn oTxCBZpjLoVcaf+9vcdNLLqdFnGjedTg73Fnk3NLEWKm+yYFin02gfFGpNQCabirPemr SOxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=XEa6rgZnUyAXDzw6k5Wm7RfYfnHAGNjNhYDmbAFVjBc=; b=WkYWpq0GauhNuMm99hYaT4codn3/OgW19lM1dlHzrQzwvdftufrDa6xIP/yclmUXRT ZPcgccSQTd9XS9BAOBHx0Xahx8AbZsJSbG0IsuimSWcNr33ElYSwPcsXk34QJeoRb30a fXFna9XL/hkV5f3/VBgtACoPOcoxSvil+oqY8UYFWnV7HzgO5h6DEP9kU/mSkr+nWCYd I7vbqZ4mrDXLsaKtQQtss+omc3/9OUBDoMoe0xsc4pt+EnZXGRIC+JKOoCmC0S08rSww iXgiZ14UIvObdSModXGhYw8YF8bdXQ2w34+9cjh+QsT0jcQZs1NL075Dc2XSWU3wLP/V xLBw== X-Gm-Message-State: APjAAAVI04Lp8L/LYwB64XuZ/64Vsv7DQiApId4Y840qCP7vszT+7IrN rrK1uGr8z8LIf4Moxzmy/e1jhICeZokFDt2/8/aOAQ== X-Received: by 2002:adf:fb4a:: with SMTP id c10mr6821472wrs.309.1556117270817; Wed, 24 Apr 2019 07:47:50 -0700 (PDT) MIME-Version: 1.0 References: <20190424141900.8883-1-tmurphy@arista.com> <20190424143246.GA24079@infradead.org> In-Reply-To: <20190424143246.GA24079@infradead.org> From: Tom Murphy Date: Wed, 24 Apr 2019 15:47:39 +0100 Message-ID: Subject: Re: [PATCH] iommu/amd: flush not present cache in iommu_map_page To: Christoph Hellwig Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Tom Murphy Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >The two conditions can go into one if statement to make this a little >more clear. Ah, yeah of course >And I'd really like to understand the unlikely - amd_iommu_np_cache >is set based on a hardware capability, so it seems rather odd to mark >it unlikely. Dynamic branch prediction really should do the right thing >here usually. Here is the commit which added it without any explanation: https://github.com/torvalds/linux/commit/270cab2426cdc6307725e4f1f46ecf8ab8e69193 should we remove it seen as there's no explanation given ? On Wed, Apr 24, 2019 at 3:32 PM Christoph Hellwig wrote: > > On Wed, Apr 24, 2019 at 03:18:59PM +0100, Tom Murphy via iommu wrote: > > check if there is a not-present cache present and flush it if there is. > > > > Signed-off-by: Tom Murphy > > --- > > drivers/iommu/amd_iommu.c | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c > > index f7cdd2ab7f11..8ef43224aae0 100644 > > --- a/drivers/iommu/amd_iommu.c > > +++ b/drivers/iommu/amd_iommu.c > > @@ -1636,6 +1636,12 @@ static int iommu_map_page(struct protection_domain *dom, > > pte[i] = __pte; > > > > update_domain(dom); > > + if (!dom->updated) { > > + if (unlikely(amd_iommu_np_cache)) { > > + domain_flush_pages(dom, bus_addr, page_size); > > + domain_flush_complete(dom); > > + } > > + } > > The two conditions can go into one if statement to make this a little > more clear. > > And I'd really like to understand the unlikely - amd_iommu_np_cache > is set based on a hardware capability, so it seems rather odd to mark > it unlikely. Dynamic branch prediction really should do the right thing > here usually.