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[209.132.180.67]) by mx.google.com with ESMTP id ci5si20829919plb.145.2019.04.24.12.35.30; Wed, 24 Apr 2019 12:35:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l4AFDOlC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729810AbfDXMZx (ORCPT + 99 others); Wed, 24 Apr 2019 08:25:53 -0400 Received: from mail-qk1-f196.google.com ([209.85.222.196]:37384 "EHLO mail-qk1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727270AbfDXMZx (ORCPT ); Wed, 24 Apr 2019 08:25:53 -0400 Received: by mail-qk1-f196.google.com with SMTP id c1so10678207qkk.4 for ; Wed, 24 Apr 2019 05:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=clPB49k5bUNWi1l9QLb30EX4SpuEGDe/C4dN/7k8mBs=; b=l4AFDOlCisAsBDJKMyKqJkIulWY5JOkKmxfzXD6I1tcgfe2nUxJ4JuS4bu+lIVMgk4 tF7arAKFnlTKSShbrbOju7vRQzJZVylYT/dc9yo7JDSIORgD2EcqjgxnDij0vASxQk6k JUF9Le0nqTfLemixWBLl8rfxPF8lREjEGyL4SUvcCrplDcqYyw1BSuMS/AOn4HOUh6oi xbN2As/9VpO331UXOhh9X/S8pNFVP7reu0e+OnK/Setf1vN5GdKJOt9sZ7KNuCDuWmWX v5O/RvhekPiMOFeXoaP9RoZT5mo3teJNj5JhlQ7qTSIWabZPYdtOtkAht2M/VI3xp/sw 682w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=clPB49k5bUNWi1l9QLb30EX4SpuEGDe/C4dN/7k8mBs=; b=KZ2Tq+en8QiAlghg+llfPs5Ifm51FNXxCBp4nl6OX6cNeH0QGZ7Nr2JJBIcUc4HMYh ATu1aGPoiEn3KeNwZ6gEiZQUuo8HUXiy4ESjH0XWMi6mCx5rCuyY7jqxLXi/2W9/KAIx aVXzpHEkNzrpV7Hc0sHMGK1rw/rE8s7mcpigvJ+RExkN1OdDIIg/9OvHa1VukYTw4528 0ORec+SgvSFowEFWHBm4oPfUNRl/UL3VPvTb8QviUdx2ZlhKP0lzgyYt7ICy3koERXWP 7udnea9pIctYTafDphyYigWFp7qJq4YMEGpwfczA16xT2R9rb4ynkSoD9V1drmCkYsx4 2itA== X-Gm-Message-State: APjAAAVEPp/CeDQ6j2+CWRH20vZmGUQGc1lfrdvp9zk7SqyJK4XTbGcB NMvHPBtkEyO+lKPJgbfhot4GeBOZUHkXprhqXpdSbQ== X-Received: by 2002:a37:274a:: with SMTP id n71mr19416460qkn.228.1556108752170; Wed, 24 Apr 2019 05:25:52 -0700 (PDT) MIME-Version: 1.0 References: <1554103457-29595-1-git-send-email-yannick.fertre@st.com> <7ff86999-02e5-ef48-221c-a5e0e61eb2fd@st.com> In-Reply-To: <7ff86999-02e5-ef48-221c-a5e0e61eb2fd@st.com> From: Benjamin Gaignard Date: Wed, 24 Apr 2019 14:25:41 +0200 Message-ID: Subject: Re: [PATCH] drm/stm: ltdc: update planes at next vblank to avoid partial refresh To: Philippe CORNU Cc: Yannick FERTRE , Vincent ABRIOU , David Airlie , Daniel Vetter , Maxime Coquelin , Alexandre TORGUE , "dri-devel@lists.freedesktop.org" , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le lun. 1 avr. 2019 =C3=A0 11:22, Philippe CORNU a = =C3=A9crit : > > Dear Yannick, > Thank you for your patch, works fine, > > Acked-by: Philippe Cornu > Applied on drm-misc-next, Thanks, Benjamin > Philippe :-) > > On 4/1/19 9:24 AM, Yannick Fertr=C3=A9 wrote: > > Plane updates must be synchronized on vblank with the shadow register m= echanism > > to avoid partial refresh on screen. > > > > Signed-off-by: Yannick Fertr=C3=A9 > > --- > > drivers/gpu/drm/stm/ltdc.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c > > index b1741a9..c2d0800 100644 > > --- a/drivers/gpu/drm/stm/ltdc.c > > +++ b/drivers/gpu/drm/stm/ltdc.c > > @@ -426,8 +426,8 @@ static void ltdc_crtc_atomic_enable(struct drm_crtc= *crtc, > > /* Enable IRQ */ > > reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); > > > > - /* Immediately commit the planes */ > > - reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); > > + /* Commit shadow registers =3D update planes at next vblank */ > > + reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); > > > > /* Enable LTDC */ > > reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); > > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel