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From:   Paul Burton <paul.burton@mips.com>
To:     Peter Zijlstra <peterz@infradead.org>
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Subject: Re: [RFC][PATCH 1/5] mips/atomic: Fix cmpxchg64 barriers
Thread-Topic: [RFC][PATCH 1/5] mips/atomic: Fix cmpxchg64 barriers
Thread-Index: AQHU+pvwawy65CxsF0GOpcWZvtS0jqZLzDwA
Date:   Wed, 24 Apr 2019 21:00:25 +0000
Message-ID: <20190424210019.knq4nijg3xoqxzhg@pburton-laptop>
References: <20190424123656.484227701@infradead.org>
 <20190424124421.579563933@infradead.org>
In-Reply-To: <20190424124421.579563933@infradead.org>
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Hi Peter,

On Wed, Apr 24, 2019 at 02:36:57PM +0200, Peter Zijlstra wrote:
> There were no memory barriers on cmpxchg64() _at_all_. Fix this.

This does looks problematic, but it's worth noting that this code path
is only applicable to 32b kernels running on 64b CPUs which is pretty
rare. The commit message as-is suggests to me that all configurations
are broken, which isn't the case (at least, not in this respect :) ).

>=20
> Cc: Paul Burton <paul.burton@mips.com>
> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> ---
>  arch/mips/include/asm/cmpxchg.h |    6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>=20
> --- a/arch/mips/include/asm/cmpxchg.h
> +++ b/arch/mips/include/asm/cmpxchg.h
> @@ -290,9 +290,11 @@ static inline unsigned long __cmpxchg64(
>  	 * will cause a build error unless cpu_has_64bits is a		\
>  	 * compile-time constant 1.					\
>  	 */								\
> -	if (cpu_has_64bits && kernel_uses_llsc)				\
> +	if (cpu_has_64bits && kernel_uses_llsc) {			\
> +		smp_mb__before_llsc();					\
>  		__res =3D __cmpxchg64((ptr), __old, __new);		\
> -	else								\
> +		smp_llsc_mb();						\
> +	} else								\
>  		__res =3D __cmpxchg64_unsupported();			\

It would be good to also add braces around the else block, and I believe
checkpatch should be complaining about that ("braces {} should be used
on all arms of this statement").

Thanks,
    Paul

>  									\
>  	__res;								\
>=20
>=20