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From:   Paul Burton <paul.burton@mips.com>
To:     Peter Zijlstra <peterz@infradead.org>
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Subject: Re: [RFC][PATCH 4/5] mips/atomic: Fix smp_mb__{before,after}_atomic()
Thread-Topic: [RFC][PATCH 4/5] mips/atomic: Fix
 smp_mb__{before,after}_atomic()
Thread-Index: AQHU+pvw+cZO+u6L3EeyssGPr9Lw/6ZL0vSA
Date:   Wed, 24 Apr 2019 21:24:31 +0000
Message-ID: <20190424212422.bykvyho3jqw6jz6w@pburton-laptop>
References: <20190424123656.484227701@infradead.org>
 <20190424124421.751367532@infradead.org>
In-Reply-To: <20190424124421.751367532@infradead.org>
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Hi Peter,

On Wed, Apr 24, 2019 at 02:37:00PM +0200, Peter Zijlstra wrote:
> --- a/arch/mips/include/asm/barrier.h
> +++ b/arch/mips/include/asm/barrier.h
> @@ -230,9 +238,6 @@
>  #define nudge_writes() mb()
>  #endif
> =20
> -#define __smp_mb__before_atomic()	__smp_mb__before_llsc()
> -#define __smp_mb__after_atomic()	smp_llsc_mb()
> -
>  /*
>   * Some Loongson 3 CPUs have a bug wherein execution of a memory access =
(load,
>   * store or pref) in between an ll & sc can cause the sc instruction to

I think this bit should be part of patch 3, where you currently add a
second definition of these 2 macros.

Otherwise this one looks reasonable to me.

Thanks,
    Paul