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In-Reply-To: <20190422091509.3181-1-andy.tang@nxp.com>
References: <20190422091509.3181-1-andy.tang@nxp.com>
Cc:     robh+dt@kernel.org, mark.rutland@arm.com,
        linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, Yuantian Tang <andy.tang@nxp.com>
From:   Stephen Boyd <sboyd@kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: qoriq-clock: add more PLL divider clocks support
To:     andy.tang@nxp.com, mturquette@baylibre.com
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Quoting andy.tang@nxp.com (2019-04-22 02:15:08)
> From: Yuantian Tang <andy.tang@nxp.com>
>=20
> More PLL divider clocks are needed by clock consumer IP. So update
> the PLL divider description to make it more general.
>=20
> Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
> ---

Applied to clk-next