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Cc:     robh+dt@kernel.org, mark.rutland@arm.com,
        linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, Yuantian Tang <andy.tang@nxp.com>
From:   Stephen Boyd <sboyd@kernel.org>
Subject: Re: [PATCH 2/2] clk: qoriq: add more PLL divider clocks support
To:     andy.tang@nxp.com, mturquette@baylibre.com
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Date:   Thu, 25 Apr 2019 11:23:05 -0700
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Quoting andy.tang@nxp.com (2019-04-22 02:15:09)
> From: Yuantian Tang <andy.tang@nxp.com>
>=20
> More PLL divider clocks are needed by clock consumer IP. So enlarge
> the PLL divider array to accommodate more divider clocks.
>=20
> Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
> ---

Applied to clk-next