Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp2298014yba; Thu, 25 Apr 2019 14:02:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqz0eOQjeVSz9Glettmip0NNmvgDzXOnnF8QZ0K92VGSDr0ldDNpQ+qQq2UBoSU4VIgtOBP7 X-Received: by 2002:a63:1364:: with SMTP id 36mr34747953pgt.436.1556226177935; Thu, 25 Apr 2019 14:02:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556226177; cv=none; d=google.com; s=arc-20160816; b=qhaCcULplldktv+R3FKhcT4AuSFFcJHSowXb4ha7wgOJ47+VkvQ8KeOAXQZA2Uc2Tf UFkb1IbN11fNI/fLZhGHyNJ0zZUQkGMDjeZB+L3cjEgpA52D3PNy5RAxIVnQIwb62+tO 9384Oe8/SOS4H96LYYuua/heRDQZNDzBK9bzP1OTBw17PKxGUjgTR1w9H9kfMo2ygvut KhrYm2B6ZJjlW9GfU//gl5YgEx3ALQxTQn8hoN9I/LqJyS8Snd1U4TuUJKqPnnT+bfPs LzspBR6zqgj30qDfmcYuiHg6wn/3TVlE8FKWeTTl+Saw1gLdS1Rd6Fw3d4aRFx3wy+Lr H+CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:cc:to:subject :message-id:date:from:in-reply-to:references:mime-version :dkim-signature; bh=m5za7n1oEjeLIknb6phOrUrhUG4/hlL+Pwkng0870GE=; b=w1O3fXm0IjLj4nXk0YUFYH7o+TJnky/kJG2cgFdeA3Jk0OGjlqMnkhF50BG0je6nEY 9QHhSo6lXElLvmRiXyf9zYuuDVmRk7l5qulYtUizKeaEc6nEH/Qf9sLgAFPC/HvFJhGN MibC0fATC7g3Ih3NpRpbcn+KmhSWEfPHbuFzNpfcVBCc/z6NLc6L1r4Ef68BZtQ7djLm 1ch8mdjzaCNbYsJ+vteGYHxUWppkLQN/+rkqTemQMJRbJD88AinWEyybeAqmTmoF37HL gnxuQHuLQkNt1IdMFhmIHZOWIk4oy3N3dX6gxS/T0arAXW/9GZPo5tosCPQJcJO2/gfa /4Yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=AeH32e9g; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i24si22209384pgh.434.2019.04.25.14.02.40; Thu, 25 Apr 2019 14:02:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=AeH32e9g; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730082AbfDYRtn (ORCPT + 99 others); Thu, 25 Apr 2019 13:49:43 -0400 Received: from mail.kernel.org ([198.145.29.99]:55056 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730040AbfDYRtn (ORCPT ); Thu, 25 Apr 2019 13:49:43 -0400 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 163FE212F5 for ; Thu, 25 Apr 2019 17:49:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1556214582; bh=k7j/1g7qfQNqTMzadjTDghyn+ZldaWg22WWJRpeAVjE=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=AeH32e9gKFK/kCCx4QBmNaIi9VoX2FsuBBARmXxzEEqAq3z+dTBgxGXKkfzqgpS2g FQvNLn104ZeAtZnGYEoMQykDgBtX2JkgpaAcwQf50dFeJYDfVGi/ds5EZelPMhPuJQ LX+mBbOazigTfZCu8jlaN1AH+IO5vQx7DoIF8kgQ= Received: by mail-wm1-f47.google.com with SMTP id h18so438247wml.1 for ; Thu, 25 Apr 2019 10:49:41 -0700 (PDT) X-Gm-Message-State: APjAAAWVYnb4UGihoVZ+b7ZFU9vfQyVsqV+eTYC6zbIUjryFXhZ7RgDr SO2SDXQG7rvHjuGJJ0ATnjiyK2V+Uvt1n+NGN1p4+g== X-Received: by 2002:a7b:c182:: with SMTP id y2mr4262844wmi.83.1556214579825; Thu, 25 Apr 2019 10:49:39 -0700 (PDT) MIME-Version: 1.0 References: <20190422185805.1169-1-rick.p.edgecombe@intel.com> <20190422185805.1169-4-rick.p.edgecombe@intel.com> <20190425162620.GA5199@zn.tnic> In-Reply-To: From: Andy Lutomirski Date: Thu, 25 Apr 2019 10:49:27 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 03/23] x86/mm: Introduce temporary mm structs To: Nadav Amit Cc: Andy Lutomirski , Rick Edgecombe , Ingo Molnar , LKML , X86 ML , "H. Peter Anvin" , Thomas Gleixner , Dave Hansen , Peter Zijlstra , Damian Tometzki , linux-integrity , LSM List , Andrew Morton , Kernel Hardening , Linux-MM , Will Deacon , Ard Biesheuvel , Kristen Carlson Accardi , "Dock, Deneen T" , Kees Cook , Dave Hansen , Borislav Petkov Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 25, 2019 at 10:37 AM Nadav Amit wrote: > > > On Apr 25, 2019, at 9:26 AM, Borislav Petkov wrote: > > > > On Mon, Apr 22, 2019 at 11:57:45AM -0700, Rick Edgecombe wrote: > >> From: Andy Lutomirski > >> > >> Using a dedicated page-table for temporary PTEs prevents other cores > >> from using - even speculatively - these PTEs, thereby providing two > >> benefits: > >> > >> (1) Security hardening: an attacker that gains kernel memory writing > >> abilities cannot easily overwrite sensitive data. > >> > >> (2) Avoiding TLB shootdowns: the PTEs do not need to be flushed in > >> remote page-tables. > >> > >> To do so a temporary mm_struct can be used. Mappings which are private > >> for this mm can be set in the userspace part of the address-space. > >> During the whole time in which the temporary mm is loaded, interrupts > >> must be disabled. > >> > >> The first use-case for temporary mm struct, which will follow, is for > >> poking the kernel text. > >> > >> [ Commit message was written by Nadav Amit ] > >> > >> Cc: Kees Cook > >> Cc: Dave Hansen > >> Acked-by: Peter Zijlstra (Intel) > >> Reviewed-by: Masami Hiramatsu > >> Tested-by: Masami Hiramatsu > >> Signed-off-by: Andy Lutomirski > >> Signed-off-by: Nadav Amit > >> Signed-off-by: Rick Edgecombe > >> --- > >> arch/x86/include/asm/mmu_context.h | 33 ++++++++++++++++++++++++++++++ > >> 1 file changed, 33 insertions(+) > >> > >> diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm= /mmu_context.h > >> index 19d18fae6ec6..d684b954f3c0 100644 > >> --- a/arch/x86/include/asm/mmu_context.h > >> +++ b/arch/x86/include/asm/mmu_context.h > >> @@ -356,4 +356,37 @@ static inline unsigned long __get_current_cr3_fas= t(void) > >> return cr3; > >> } > >> > >> +typedef struct { > >> + struct mm_struct *prev; > >> +} temp_mm_state_t; > >> + > >> +/* > >> + * Using a temporary mm allows to set temporary mappings that are not= accessible > >> + * by other cores. Such mappings are needed to perform sensitive memo= ry writes > > > > s/cores/CPUs/g > > > > Yeah, the concept of a thread of execution we call a CPU in the kernel, > > I'd say. No matter if it is one of the hyperthreads or a single thread > > in core. > > > >> + * that override the kernel memory protections (e.g., W^X), without e= xposing the > >> + * temporary page-table mappings that are required for these write op= erations to > >> + * other cores. > > > > Ditto. > > > >> Using temporary mm also allows to avoid TLB shootdowns when the > > > > Using a .. > > > >> + * mapping is torn down. > >> + * > > > > Nice commenting. > > > >> + * Context: The temporary mm needs to be used exclusively by a single= core. To > >> + * harden security IRQs must be disabled while the temporary= mm is > > ^ > > , > > > >> + * loaded, thereby preventing interrupt handler bugs from ov= erriding > >> + * the kernel memory protection. > >> + */ > >> +static inline temp_mm_state_t use_temporary_mm(struct mm_struct *mm) > >> +{ > >> + temp_mm_state_t state; > >> + > >> + lockdep_assert_irqs_disabled(); > >> + state.prev =3D this_cpu_read(cpu_tlbstate.loaded_mm); > >> + switch_mm_irqs_off(NULL, mm, current); > >> + return state; > >> +} > >> + > >> +static inline void unuse_temporary_mm(temp_mm_state_t prev) > >> +{ > >> + lockdep_assert_irqs_disabled(); > >> + switch_mm_irqs_off(NULL, prev.prev, current); > > > > I think this code would be more readable if you call that > > temp_mm_state_t variable "temp_state" and the mm_struct pointer "mm" an= d > > then you have: > > > > switch_mm_irqs_off(NULL, temp_state.mm, current); > > > > And above you'll have: > > > > temp_state.mm =3D ... > > Andy, please let me know whether you are fine with this change and I=E2= =80=99ll > incorporate it. I'm okay with it.