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Date:   Thu, 25 Apr 2019 14:11:02 -0700 (PDT)
Subject:     Re: [PATCH 2/3] riscv: Add support for perf registers sampling
In-Reply-To: <69322515ac3fcba8af004039f44473cec5ecbdcc.1554961908.git.han_mao@c-sky.com>
CC:     linux-kernel@vger.kernel.org, han_mao@c-sky.com
From:   Palmer Dabbelt <palmer@sifive.com>
To:     han_mao@c-sky.com
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On Thu, 11 Apr 2019 00:53:49 PDT (-0700), han_mao@c-sky.com wrote:
> This patch implements the perf registers sampling and validation API
> for riscv arch. The valid registers and their register ID are defined in
> perf_regs.h. Perf tool can backtrace in userspace with unwind library
> and the registers/user stack dump support.
>
> Signed-off-by: Mao Han <han_mao@c-sky.com>
>
> CC: Palmer Dabbelt <palmer@sifive.com>
> ---
>  arch/riscv/Kconfig                      |  2 ++
>  arch/riscv/include/uapi/asm/perf_regs.h | 42 +++++++++++++++++++++++++++++++
>  arch/riscv/kernel/Makefile              |  1 +
>  arch/riscv/kernel/perf_regs.c           | 44 +++++++++++++++++++++++++++++++++
>  4 files changed, 89 insertions(+)
>  create mode 100644 arch/riscv/include/uapi/asm/perf_regs.h
>  create mode 100644 arch/riscv/kernel/perf_regs.c
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index eb56c82..effd157 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -33,6 +33,8 @@ config RISCV
>  	select HAVE_DMA_CONTIGUOUS
>  	select HAVE_FUTEX_CMPXCHG if FUTEX
>  	select HAVE_PERF_EVENTS
> +	select HAVE_PERF_REGS
> +	select HAVE_PERF_USER_STACK_DUMP
>  	select HAVE_SYSCALL_TRACEPOINTS
>  	select IRQ_DOMAIN
>  	select RISCV_ISA_A if SMP
> diff --git a/arch/riscv/include/uapi/asm/perf_regs.h b/arch/riscv/include/uapi/asm/perf_regs.h
> new file mode 100644
> index 0000000..ce48987
> --- /dev/null
> +++ b/arch/riscv/include/uapi/asm/perf_regs.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +// Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd.
> +
> +#ifndef _ASM_RISCV_PERF_REGS_H
> +#define _ASM_RISCV_PERF_REGS_H
> +
> +enum perf_event_riscv_regs {
> +	PERF_REG_RISCV_PC,
> +	PERF_REG_RISCV_RA,
> +	PERF_REG_RISCV_SP,
> +	PERF_REG_RISCV_GP,
> +	PERF_REG_RISCV_TP,
> +	PERF_REG_RISCV_T0,
> +	PERF_REG_RISCV_T1,
> +	PERF_REG_RISCV_T2,
> +	PERF_REG_RISCV_S0,
> +	PERF_REG_RISCV_S1,
> +	PERF_REG_RISCV_A0,
> +	PERF_REG_RISCV_A1,
> +	PERF_REG_RISCV_A2,
> +	PERF_REG_RISCV_A3,
> +	PERF_REG_RISCV_A4,
> +	PERF_REG_RISCV_A5,
> +	PERF_REG_RISCV_A6,
> +	PERF_REG_RISCV_A7,
> +	PERF_REG_RISCV_S2,
> +	PERF_REG_RISCV_S3,
> +	PERF_REG_RISCV_S4,
> +	PERF_REG_RISCV_S5,
> +	PERF_REG_RISCV_S6,
> +	PERF_REG_RISCV_S7,
> +	PERF_REG_RISCV_S8,
> +	PERF_REG_RISCV_S9,
> +	PERF_REG_RISCV_S10,
> +	PERF_REG_RISCV_S11,
> +	PERF_REG_RISCV_T3,
> +	PERF_REG_RISCV_T4,
> +	PERF_REG_RISCV_T5,
> +	PERF_REG_RISCV_T6,
> +	PERF_REG_RISCV_MAX,
> +};

Is it expected this eventually supports floating-point and vector registers?
If so, how do we make this extensible?

> +#endif /* _ASM_RISCV_PERF_REGS_H */
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index dd2ba44..024badc 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
> @@ -39,5 +39,6 @@ obj-$(CONFIG_DYNAMIC_FTRACE)	+= mcount-dyn.o
>
>  obj-$(CONFIG_PERF_EVENTS)	+= perf_event.o
>  obj-$(CONFIG_PERF_EVENTS)	+= perf_callchain.o
> +obj-$(CONFIG_HAVE_PERF_REGS)	+= perf_regs.o
>
>  clean:
> diff --git a/arch/riscv/kernel/perf_regs.c b/arch/riscv/kernel/perf_regs.c
> new file mode 100644
> index 0000000..03d7ac3
> --- /dev/null
> +++ b/arch/riscv/kernel/perf_regs.c
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd.
> +
> +#include <linux/errno.h>
> +#include <linux/kernel.h>
> +#include <linux/perf_event.h>
> +#include <linux/bug.h>
> +#include <asm/perf_regs.h>
> +#include <asm/ptrace.h>
> +
> +u64 perf_reg_value(struct pt_regs *regs, int idx)
> +{
> +	if (WARN_ON_ONCE((u32)idx >= PERF_REG_RISCV_MAX))
> +		return 0;
> +
> +	return ((long *)regs)[idx];
> +}
> +
> +#define REG_RESERVED (~((1ULL << PERF_REG_RISCV_MAX) - 1))
> +
> +int perf_reg_validate(u64 mask)
> +{
> +	if (!mask || mask & REG_RESERVED)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +u64 perf_reg_abi(struct task_struct *task)
> +{
> +#if __riscv_xlen == 64
> +	return PERF_SAMPLE_REGS_ABI_64;
> +#else
> +	return PERF_SAMPLE_REGS_ABI_32;
> +#endif
> +}
> +
> +void perf_get_regs_user(struct perf_regs *regs_user,
> +			struct pt_regs *regs,
> +			struct pt_regs *regs_user_copy)
> +{
> +	regs_user->regs = task_pt_regs(current);
> +	regs_user->abi = perf_reg_abi(current);
> +}