Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp41538yba; Thu, 25 Apr 2019 17:37:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqxJ31425S8Eac/V70TeIa+ICeKHbEbnVUg2yqRyXTgylAZdQ05eLIjjlaOW5TbcrnaeENU3 X-Received: by 2002:a17:902:2702:: with SMTP id c2mr42590859plb.37.1556239066987; Thu, 25 Apr 2019 17:37:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556239066; cv=none; d=google.com; s=arc-20160816; b=Y1lw/c6tKfSBYpYlQXBrYoMiKUF9g/4l23kYiUcu3jHIKijDmxCl6V8346XYVoe+bh ioxGrGjxUIMEO9WMC4JDH+dOUyDK0Aq/UriefDIGaWaqx40hOQbbPcNmM1rLSZ2GEL+3 WGHcFghsEo7KtuEFqx/WewTyC0YtdG5LyOamtncXG+k8wpykp6n9LlodTOFWvdY11efN yU+MCXOhcDHDwPVRdrEx86TdSBcdIUgpQodj0hkbIZoRoR/uEYkeZZGzIQnJcn4CEaCW kkOGLpfii3pCxIf97pSOXTpUq+DtIPGt6dyHwsGnf+g4V8BWmeFt2T+lG+iVfIUUxFgK 7Utw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=bb0AB9x3iSbIjBJjeVYm27MRrtC5iBa8jXyzqa00F4Q=; b=tIxAdLUoDSpXOLwj2cM1vO4OvpLNnzo+q0YRUlK2Q8xBFucLXJOGrpnQuNDSteVzbf uiKaLXaRtqhbkPqBGHqUO+TPyksS9xaLk6YeXONDLaKlXSFLX6STzWsxWpNEtegzLZ9S czBNq+CLuswvDBJhRZ+tOPZ6YD4mg1D66iIYMJRHXNbSn+A/Tumk5glLixMirK7Cr0Lb PJuTY+vLcGe7P0qpYO8kvNBuf16P1gguYqoDBJgKhZBiDNV+PqjOjxyDjmoILBVoPUM+ HBIcSz/9cwoF62Q8o8a0ELq9cOBM29IQC1W3yL0xgZSZYreUeLBZeX5AgnPW0fasUp9h eKew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s205si22442759pgs.467.2019.04.25.17.37.32; Thu, 25 Apr 2019 17:37:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728313AbfDYU7g (ORCPT + 99 others); Thu, 25 Apr 2019 16:59:36 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:43485 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726282AbfDYU7f (ORCPT ); Thu, 25 Apr 2019 16:59:35 -0400 X-Originating-IP: 88.190.179.123 Received: from localhost (unknown [88.190.179.123]) (Authenticated sender: repk@triplefau.lt) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id DF5A16000B; Thu, 25 Apr 2019 20:59:31 +0000 (UTC) Date: Thu, 25 Apr 2019 23:08:27 +0200 From: Remi Pommarel To: Lorenzo Pieralisi Cc: Thomas Petazzoni , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Miquel Raynal Subject: Re: [PATCH] pci: aardvark: Wait for endpoint to be ready before training link Message-ID: <20190425210826.GQ2754@voidbox.localdomain> References: <20190313213752.1246-1-repk@triplefau.lt> <20190423163215.GB26523@red-moon> <20190423222917.GN2754@voidbox.localdomain> <20190424165002.GA26089@e121166-lin.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190424165002.GA26089@e121166-lin.cambridge.arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 24, 2019 at 05:50:02PM +0100, Lorenzo Pieralisi wrote: > On Wed, Apr 24, 2019 at 12:29:18AM +0200, Remi Pommarel wrote: > > Hi, > > > > On Tue, Apr 23, 2019 at 05:32:15PM +0100, Lorenzo Pieralisi wrote: > > > On Wed, Mar 13, 2019 at 10:37:52PM +0100, Remi Pommarel wrote: > > > > When configuring pcie reset pin from gpio (e.g. initially set by > > > > u-boot) to pcie function this pin goes low for a brief moment > > > > asserting the PERST# signal. Thus connected device enters fundamental > > > > reset process and link configuration can only begin after a minimal > > > > 100ms delay (see [1]). > > > > > > > > This makes sure that link is configured after at least 100ms from > > > > beginning of probe() callback (shortly after the reset pin function > > > > configuration switch through pinctrl subsytem). > > I am a bit lost, what's the connection between the probe() callback > and the reset pin function configuration ? > > Please elaborate. > So currently u-boot configures the reset pin as a GPIO set to high. The espressobin devicetree defines a default pinctrl to configure this pin as a PCIe reset function. As you can see in drivers/base/dd.c, driver_probe_device() calls really_probe() which first calls pinctrl_bind_pins() then shortly after drv->probe() callback. The pinctrl_bind_pins() function applies the default state. So here, just before drv->probe() gets called our reset pin goes from GPIO function to PCIe reset one making it going low for a short time during this transition. Because the pin goes low then gets back to high, PERST# signal is asserted then deasserted and device enters fundamental reset process just before drv->probe() is called. So in order to reduce the waiting time to a minimum I sample jiffies at the very beginning of the probe function, which is the closer spot from where PERST# is deasserted. To sum up: driver_probe_device() { ... really_probe() { ... pinctrl_bind_pins(); /* Here PERST# is asserted because pin configuration changes */ ... drv->probe(); ... } ... } > > > > > > > > [1] "PCI Express Base Specification", REV. 2.1 > > > > PCI Express, March 4 2009, 6.6.1 Conventional Reset > > > > > > > > Signed-off-by: Remi Pommarel > > > > --- > > > > drivers/pci/controller/pci-aardvark.c | 17 ++++++++++++++--- > > > > 1 file changed, 14 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > > > > index a30ae7cf8e7e..70a1023d0ef1 100644 > > > > --- a/drivers/pci/controller/pci-aardvark.c > > > > +++ b/drivers/pci/controller/pci-aardvark.c > > > > @@ -177,6 +177,9 @@ > > > > > > > > #define PIO_TIMEOUT_MS 1 > > > > > > > > +/* Endpoint can take up to 100ms to be ready after a reset */ > > > > +#define ENDPOINT_RST_MS 100 > > > > + > > > > #define LINK_WAIT_MAX_RETRIES 10 > > > > #define LINK_WAIT_USLEEP_MIN 90000 > > > > #define LINK_WAIT_USLEEP_MAX 100000 > > > > @@ -242,8 +245,10 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie) > > > > return -ETIMEDOUT; > > > > } > > > > > > > > -static void advk_pcie_setup_hw(struct advk_pcie *pcie) > > > > +static void > > > > +advk_pcie_setup_hw(struct advk_pcie *pcie, unsigned long ep_rdy_time) > > > > > > Nit: I prefer the prototype to be in one line, I wrap it for you. > > > > > > I am wondering why you need to pass in ep_rdy_time parameter when you > > > can easily compute it in the function itself. > > > > > > > The only reason for that is because the sooner I get the jiffies the > > lower the delay has to be. I was trying to reduce the impact of this > > delay to a minimum, but maybe the improvement is not worth it. > > That should just be (roughly) some microseconds unless there is > something I am missing. Try to measure it :) So doing that I do a msleep() of around 75-80ms instead of 100ms. So, yes, are 20ms enough to justify that, or should we just go with a plain msleep(100) to improve legibility. -- Remi