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[209.132.180.67]) by mx.google.com with ESMTP id r10si22870847pgp.30.2019.04.26.00.12.19; Fri, 26 Apr 2019 00:12:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ThFeg9+t; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726077AbfDZHLO (ORCPT + 99 others); Fri, 26 Apr 2019 03:11:14 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:38903 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725947AbfDZHLN (ORCPT ); Fri, 26 Apr 2019 03:11:13 -0400 Received: by mail-lj1-f194.google.com with SMTP id p14so1944203ljg.5 for ; Fri, 26 Apr 2019 00:11:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=NeYeNXiQHZAi5lbF4OrYrEU5AHV7RHK83sfErcveMd8=; b=ThFeg9+tZ2EoGJnQRyKkvSy/1GJtBSZW2yzyjhFbMW4hBlv5rYeL2pDSZCopL5IoKk 90au01UwY5E0frNJr/mhrFynFT+L8vpuxMdxbRX6CxBHHSzfFEClA31Utljz8nsDMNf0 vqWf6B+U153ScsfqNLrUAquGc5KPRDJClSHWtB60KtxuMWm/3pqdfsV0tPUXI31H3sDQ RA5D2nmH0ZC0slXftTdIoW83yK2Qc9QR3U8WuYFqjBlvfNS2lsockuIMB0ADQI1Rvprn lZJMx/zKTEDuA5CLy9naEUldEgSNbsibxv2sIbG5PZ+XSMl8u4FFmT8T2liS8rl0um9h vmIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NeYeNXiQHZAi5lbF4OrYrEU5AHV7RHK83sfErcveMd8=; b=IGUpVlZqu5OYqVoIgZQtov/8VsuZhEWwUqbgT3Q2NClAMyhaTKtP1KJBQMWiyL3hPZ gtPTR5QeEARMsYfEBR+qrKhJUXLOuCC58JPEhRuNQ9ALRx3PKKZx7w7p61vWCk4mT1Va G1cESIn0tZSF1WWbMucxKODbcoZjefRoaypS1wqb9PUXu0KaMfaUqBmLl4OVqpH6YRm+ LVOu24WohEFIFH58NhYusfrRbJcIvznxM3JFzkc2seAsmB5cgspr4cqrIBRpLV0ARpd8 uCmfDvy6Ca20/iMvX5hWbNuEQ5aZ5jknvdr7yTyPZWFKmKyYgaengjS0xlHAHnjZkRcg vDJg== X-Gm-Message-State: APjAAAVHYIogwuG//+UlqcZqvK6fzXAIb0Xje19KVtlC+9iKLAUzvv+i vxJSUicJpE4Lc39vhAZHtojdYMR6J43m62bcBRWCyw== X-Received: by 2002:a2e:8703:: with SMTP id m3mr22735299lji.107.1556262671816; Fri, 26 Apr 2019 00:11:11 -0700 (PDT) MIME-Version: 1.0 References: <1556247378-3335-1-git-send-email-kyarlagadda@nvidia.com> <1556247378-3335-2-git-send-email-kyarlagadda@nvidia.com> In-Reply-To: <1556247378-3335-2-git-send-email-kyarlagadda@nvidia.com> From: Linus Walleij Date: Fri, 26 Apr 2019 09:11:00 +0200 Message-ID: Subject: Re: [PATCH 2/2] pinctrl: tegra: Add Tegra194 pinmux driver To: Krishna Yarlagadda , Stephen Warren Cc: "thierry.reding@gmail.com" , Jon Hunter , "linux-kernel@vger.kernel.org" , "open list:GPIO SUBSYSTEM" , linux-tegra@vger.kernel.org, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Peter De Schrijver , Joseph Lo , Suresh Mangipudi , Laxman Dewangan , vidyas@nvidia.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 26, 2019 at 4:56 AM Krishna Yarlagadda wrote: > Tegra194 has PCIE L5 rst and clkreq pins which need to be controlled > dynamically at runtime. This driver supports change pinmux for these > pins. Pinmux for rest of the pins is set statically by bootloader and > will not be changed by this driver > > Signed-off-by: Krishna Yarlagadda > Signed-off-by: Suresh Mangipudi Paging Stephen Warren about this patch, an ACK from Thierry would be nice too. Yours, Linus Walleij