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Date:   Fri, 26 Apr 2019 18:16:26 +0100
From:   Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
Cc:     Remi Pommarel <repk@triplefau.lt>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org,
        Miquel Raynal <miquel.raynal@bootlin.com>
Subject: Re: [PATCH] pci: aardvark: Wait for endpoint to be ready before
 training link
Message-ID: <20190426171626.GA11753@e121166-lin.cambridge.arm.com>
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 <20190423163215.GB26523@red-moon>
 <20190423222917.GN2754@voidbox.localdomain>
 <20190424165002.GA26089@e121166-lin.cambridge.arm.com>
 <20190425210826.GQ2754@voidbox.localdomain>
 <20190426161050.GA189964@google.com>
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On Fri, Apr 26, 2019 at 11:10:50AM -0500, Bjorn Helgaas wrote:
> On Thu, Apr 25, 2019 at 11:08:27PM +0200, Remi Pommarel wrote:
> > On Wed, Apr 24, 2019 at 05:50:02PM +0100, Lorenzo Pieralisi wrote:
> > > On Wed, Apr 24, 2019 at 12:29:18AM +0200, Remi Pommarel wrote:
> > > > On Tue, Apr 23, 2019 at 05:32:15PM +0100, Lorenzo Pieralisi wrote:
> > > > > On Wed, Mar 13, 2019 at 10:37:52PM +0100, Remi Pommarel wrote:
> > > > > > When configuring pcie reset pin from gpio (e.g. initially set by
> > > > > > u-boot) to pcie function this pin goes low for a brief moment
> > > > > > asserting the PERST# signal. Thus connected device enters fundamental
> > > > > > reset process and link configuration can only begin after a minimal
> > > > > > 100ms delay (see [1]).
> > > > > > 
> > > > > > This makes sure that link is configured after at least 100ms from
> > > > > > beginning of probe() callback (shortly after the reset pin function
> > > > > > configuration switch through pinctrl subsytem).
> > > 
> > > I am a bit lost, what's the connection between the probe() callback
> > > and the reset pin function configuration ?
> > 
> > So currently u-boot configures the reset pin as a GPIO set to high. The
> > espressobin devicetree defines a default pinctrl to configure this pin
> > as a PCIe reset function.
> > 
> > As you can see in drivers/base/dd.c, driver_probe_device() calls
> > really_probe() which first calls pinctrl_bind_pins() then shortly after
> > drv->probe() callback. The pinctrl_bind_pins() function applies the
> > default state. So here, just before drv->probe() gets called our reset
> > pin goes from GPIO function to PCIe reset one making it going low for a
> > short time during this transition.
> > 
> > Because the pin goes low then gets back to high, PERST# signal is
> > asserted then deasserted and device enters fundamental reset process
> > just before drv->probe() is called. So in order to reduce the waiting
> > time to a minimum I sample jiffies at the very beginning of the probe
> > function, which is the closer spot from where PERST# is deasserted.
> > 
> > To sum up:
> > 
> > driver_probe_device() {
> > 	...
> > 	really_probe() {
> > 		...
> > 		pinctrl_bind_pins(); /* Here PERST# is asserted because pin configuration changes */
> > 		...
> > 		drv->probe();
> 
> Ah, I see.  Hmmm.  This definitely warrants a comment in
> advk_pcie_probe() about the connection.
> 
> I appreciate that ab78029ecc34 ("drivers/pinctrl: grab default handles
> from device core") saves some boilerplate from drivers, but ... at the
> same time, it makes for some non-obvious implicit connections like
> this.  I'm not sure whether having the boilerplate or the comment is
> worse.  But I'm pretty sure the "no boilerplate, no comment" option is
> the worst of the three :)

Yes, it is horrible. Can't this be managed explicitly through
the reset core code (drivers/reset/) ? I really do not like
this implicit reset going on behind the scenes, I will have
a look to understand how other controllers handle this.

Lorenzo