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Date: Tue, 10 Jul 2001 15:35:26 -0400
From: Brian Gerst <bgerst@didntduck.org>
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To: Chris Wedgwood <cw@f00f.org>
CC: Jesse Pollard <pollard@tomcat.admin.navo.hpc.mil>, ttabi@interactivesi.com,
        linux-kernel@vger.kernel.org
Subject: Re: What is the truth about Linux 2.4's RAM limitations?
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Chris Wedgwood wrote:
> 
> On Tue, Jul 10, 2001 at 02:28:54PM -0400, Brian Gerst wrote:
> 
>     Jesse Pollard wrote:
> 
>         > If the entire page table were given to a user, then a full cache
>         > flush would have to be done on every context switch and system
>         > call. That would be very slow, but would allow a full 4G address
>         > for the user.
> 
>     A full cache flush would be needed at every entry into the kernel,
>     including hardware interrupts.  Very poor for performance.
> 
> Why would a cache flush be necessary at all? I assume ia32 caches
> where physically not virtually mapped?

I meant TLB flush, sorry.

--

				Brian Gerst
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