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Date: Tue, 10 Jul 2001 15:07:11 -0700
To: Jesse Pollard <pollard@tomcat.admin.navo.hpc.mil>, cw@f00f.org,
        Brian Gerst <bgerst@didntduck.org>
From: Jonathan Lundell <jlundell@pobox.com>
Subject: Re: What is the truth about Linux 2.4's RAM limitations?
Cc: Jesse Pollard <pollard@tomcat.admin.navo.hpc.mil>, ttabi@interactivesi.com,
        linux-kernel@vger.kernel.org
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At 4:49 PM -0500 2001-07-10, Jesse Pollard wrote:
>  >     A full cache flush would be needed at every entry into the kernel,
>>      including hardware interrupts.  Very poor for performance.
>>
>>  Why would a cache flush be necessary at all? I assume ia32 caches
>>  where physically not virtually mapped?
>
>Because the entire virtual mapping is replaced by that of the kernel.
>This would invalidate the entire cache table. It was also pointed out
>that this would have to be done for every interrupt too.

If the cache were physically indexed and tagged, this would not be 
the case; changes in mapping would be irrelevant. If someone has a 
reference that describes IA-32 cache tags in detail, I'd like to know 
about it.

TLBs are another story, though on some other architectures they're 
not a problem either. UltraSPARC, for example, maps the entire kernel 
with a couple or three reserved TLB entries (at least Solaris does). 
Of course, SPARC has hardware contexts, which are helpful in this 
regard.
-- 
/Jonathan Lundell.
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