Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S261820AbVCUPb4 (ORCPT ); Mon, 21 Mar 2005 10:31:56 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S261824AbVCUPb4 (ORCPT ); Mon, 21 Mar 2005 10:31:56 -0500 Received: from 168.imtp.Ilyichevsk.Odessa.UA ([195.66.192.168]:53509 "HELO port.imtp.ilyichevsk.odessa.ua") by vger.kernel.org with SMTP id S261820AbVCUPan (ORCPT ); Mon, 21 Mar 2005 10:30:43 -0500 From: Denis Vlasenko To: Andi Kleen , Christoph Lameter Subject: Re: [PATCH] add a clear_pages function to clear pages of higher order Date: Mon, 21 Mar 2005 17:30:29 +0200 User-Agent: KMail/1.5.4 Cc: Dave Hansen , Andrew Morton , Linux Kernel Mailing List , Mel Gorman , linux-ia64@vger.kernel.org, Jens.Maurer@gmx.net References: <20050318192808.GB38053@muc.de> In-Reply-To: <20050318192808.GB38053@muc.de> MIME-Version: 1.0 Message-Id: <200503200220.57430.vda@port.imtp.ilyichevsk.odessa.ua> Content-Type: Multipart/Mixed; boundary="Boundary-00=_ViuPCWK3mckm+uW" Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 10153 Lines: 170 --Boundary-00=_ViuPCWK3mckm+uW Content-Type: text/plain; charset="koi8-r" Content-Transfer-Encoding: 7bit Content-Disposition: inline On Friday 18 March 2005 21:28, Andi Kleen wrote: > On Fri, Mar 18, 2005 at 07:00:06AM -0800, Christoph Lameter wrote: > > On Fri, 18 Mar 2005, Denis Vlasenko wrote: > > > > > NT stores are not about 5% increase. 200%-300%. Provided you are ok with > > > the fact that zeroed page ends up evicted from cache. Luckily, this is exactly > > > what you want with prezeroing. > > > > These are pretty significant results. Maybe its best to use non-temporal > > The differences are actually less. I do not know what Denis benchmarked, > but in my tests the difference was never more than ~10%. He got a zero > too much? No. See attached. # gcc -O2 0main.c # ./a.out Page clear/copy benchmark program. buffer size: 1 Mb Each test tried 64 times, max and min CPU cycles per page are reported. Please disregard max values. They are due to system interference only. clear_page() tests: normal_clear_page - took 44214 max,12615 min cycles per page normal_clear_page - took 18969 max,12649 min cycles per page repstosl_clear_page - took 19897 max,12655 min cycles per page movq_clear_page - took 39391 max,10782 min cycles per page movntq_clear_page - took 21612 max, 4779 min cycles per page copy_page() tests: .... I'm basically saying that 'microbenchmark-visible' performance of NT stores is 200-300% higher than 'normal' stores. BTW: cache eviction is not an intrisic property of non-temporal stores. It's merely how they're implemented in current CPUs: if NT stores hit cached line, invalidate it and push stores to bus. Else just push stores to bus without reading cacheline from RAM first. It is possible that some future CPU won't evict cacheline if NT stores happened to hit it: "if NT stores hit cached line, MODIFY it and push stores to bus". -- vda --Boundary-00=_ViuPCWK3mckm+uW Content-Type: application/x-tbz; name="page_asm.tar.bz2" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="page_asm.tar.bz2" QlpoOTFBWSZTWeFrTkYAP/n/7v6/IMB7////v//f/v////sREAAQAEEQCYAEAKhgHh33YAfV2vRu ttaJ0YrxhqQ8rddy3Y6OvOZ7vcu2rG1hQDa9re3c22m3k73mVHVMqkrsxQOhryXdwke7RcFUns1F CuEkk0ajVPU8m0p+pPNFNqepp6jQaAaNAANpGmmjQAAfqgAyD1PSCSBBBRlPKmRDAJkxMAI0wRkY Q0ZMhphGJkYjACDgAAAAGgAAAADQaAAAABkAaAAIUkiGip+qbSeTU8UyY1M1GntUepo0Gm1MR6gY g9QAekxNA9QDTQwRKBCBU9iaTSYjapsp6TCPRPSMTR6j1Gg9RpoaDRtTIBoAAAiSQE0Ag0EyGk2p tTFEbTEanpGgNNGjQDTQNNDTNTQAD4D3BThld8Q8svL20odqN2qiiN4phgEgQFmIKIdMAfX8Pl8P ldd5ayTXYqsMcL8cuBCEXcQinLsIJbMtGHMPYcmR3bnlALlFIFC5JhViJSjmQRHqCMKpMlDQUtCF RJDIwhRFKG0rgAIeJCNKplflACVhkwR6MRcViqoohQ3wu2k3ZiuZiuayIYklICIiVZCkSEJlSEaG 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