Date: Mon, 28 Mar 2005 09:46:00 -0800
From: "H. J. Lu" <hjl@lucon.org>
To: Andi Kleen <ak@muc.de>
Cc: linux kernel <linux-kernel@vger.kernel.org>
Subject: Re: i386/x86_64 segment register issuses (Re: PATCH: Fix x86 segment register access)
Message-ID: <20050328174600.GA24675@lucon.org>
References: <20050326020506.GA8068@lucon.org> <20050327222406.GA6435@lucon.org> <m14qev3h8l.fsf@muc.de>
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On Mon, Mar 28, 2005 at 05:47:06PM +0200, Andi Kleen wrote:
> "H. J. Lu" <hjl@lucon.org> writes:
> > The new assembler will disallow them since those instructions with
> > memory operand will only use the first 16bits. If the memory operand
> > is 16bit, you won't see any problems. But if the memory destinatin
> > is 32bit, the upper 16bits may have random values. The new assembler
> 
> Does it really have random values on existing x86 hardware?

The x86 hardwares will only change the first 16bits. The rest bits
are unchanged. A simple test program can verify that.

> 
> If it is a only a "theoretical" problem that does not happen
> in practice I would advise to not do the change.
> 

It depends on what the initial value in the upper bits is. The
assembler in CVS generates the same binary code as

	movw %ds,(%eax)

for

	movl %ds,(%eax)

But the previous assemblers will generate

	66 8c 18   movw   %ds,(%eax)

for

	movw %ds,(%eax)

This bug has been fixed for a while. I guess that may be why Linux
kernel uses

	movl %ds,(%eax)


H.J.
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