Date: Fri, 13 May 2005 19:42:11 -0400
From: Dave Jones <davej@redhat.com>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [RFC] Cachemap for 2.6.12rc4-mm1.  Was Re: [PATCH] enhance x86 MTRR handling
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On Fri, May 13, 2005 at 04:36:10PM -0700, H. Peter Anvin wrote:

 > The Efficeon (TM8xxx) series does have PAT.

1:1 with the Intel implementation I assume based on your earlier comments?

 > > > >+ * Note: On Athlon cpus PAT2/PAT3 & PAT6/PAT7 are both Uncacheable 
 > > since > >+ *	 there is no uncached type.
 > > > If one sets the PAT to "uncached", does one get the same function as 
 > > > "uncachable"?
 > >
 > >AIUI, only as long as we don't have an MTRR covering the same range marked 
 > >WC.
 > >It seems to be the only thing I could find documenting the differences
 > >between 'uncached' and 'uncacheable' in this context.
 > >Though I've only looked through the Intel & AMD K8 docs, I don't have
 > >the K7 ones to hand.
 > >
 > 
 > I mean, on the Athlon series, is it really necessary to use a different 
 > value?

I'd have to dig out the docs and check.

		Dave
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