Date: 15 May 2005 11:37:01 +0200
Date: Sun, 15 May 2005 11:37:01 +0200
From: Andi Kleen <ak@muc.de>
To: Lee Revell <rlrevell@joe-job.com>
Cc: Arjan van de Ven <arjan@infradead.org>,
       Alan Cox <alan@lxorguk.ukuu.org.uk>, Dave Jones <davej@redhat.com>,
       Matt Mackall <mpm@selenic.com>, Andy Isaacson <adi@hexapodia.org>,
       "Richard F. Rebel" <rrebel@whenu.com>,
       Gabor MICSKO <gmicsko@szintezis.hu>,
       Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, tytso@mit.edu
Subject: Re: Hyper-Threading Vulnerability
Message-ID: <20050515093701.GA68736@muc.de>
References: <20050513232708.GC13846@redhat.com> <1116027488.6380.55.camel@mindpipe> <1116084186.20545.47.camel@localhost.localdomain> <1116088229.8880.7.camel@mindpipe> <1116089068.6007.13.camel@laptopd505.fenrus.org> <1116093396.9141.11.camel@mindpipe> <1116093694.6007.15.camel@laptopd505.fenrus.org> <1116098504.9141.31.camel@mindpipe> <1116100126.6007.17.camel@laptopd505.fenrus.org> <1116114052.9141.38.camel@mindpipe>
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> I was under the impression that P4 and later processors do not vary the
> TSC rate when doing frequency scaling.  This is mentioned in the
> documentation for the high res timers patch.

Prescott and later do not vary TSC, but P4s before that do.
On x86-64 it is true because only Nocona is supported which has a 
pstate invariant TSC.

The latest x86-64 kernel has a special X86_CONSTANT_TSC internal
CPUID bit, which is set in that case. If some other subsystem
uses it I would recommend to port that to i386 too.

-Andi
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