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Tue, 30 Apr 2019 12:36:35 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20190430123635eusmtrp1a769c1af2c8e7eb5ae012d538ed32d44~aQLuTB59_0421804218eusmtrp1P; Tue, 30 Apr 2019 12:36:35 +0000 (GMT) X-AuditID: cbfec7f2-f13ff700000010ca-36-5cc841543dff Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id F9.12.04146.35148CC5; Tue, 30 Apr 2019 13:36:35 +0100 (BST) Received: from [106.120.51.20] (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190430123634eusmtip2007e1d3560b4714296da1244959e2a28~aQLtjzC6A0081400814eusmtip2b; Tue, 30 Apr 2019 12:36:34 +0000 (GMT) Subject: Re: [PATCH v6 01/10] clk: samsung: add needed IDs for DMC clocks in Exynos5420 To: Chanwoo Choi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com From: Lukasz Luba Message-ID: <345488e4-ba7e-1f34-e166-cb340d7f7dab@partner.samsung.com> Date: Tue, 30 Apr 2019 14:36:33 +0200 User-Agent: Mozilla/5.0 (X11; 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charset="utf-8" X-RootMTR: 20190419141940eucas1p295a1130863cf2e69476ca0ba11a8a102 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190419141940eucas1p295a1130863cf2e69476ca0ba11a8a102 References: <1555683568-20882-1-git-send-email-l.luba@partner.samsung.com> <1555683568-20882-2-git-send-email-l.luba@partner.samsung.com> <9eb04a57-3e80-b0ba-334a-927493deb969@samsung.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Chanwoo, On 4/30/19 6:47 AM, Chanwoo Choi wrote: > Hi, > > On 19. 4. 19. 오후 11:19, Lukasz Luba wrote: >> Define new IDs for clocks used by Dynamic Memory Controller in >> Exynos5422 SoC. >> >> Acked-by: Rob Herring >> Signed-off-by: Lukasz Luba >> --- >> include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- >> 1 file changed, 17 insertions(+), 1 deletion(-) >> >> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h >> index 355f469..abb1842 100644 >> --- a/include/dt-bindings/clock/exynos5420.h >> +++ b/include/dt-bindings/clock/exynos5420.h >> @@ -60,6 +60,7 @@ >> #define CLK_MAU_EPLL 159 >> #define CLK_SCLK_HSIC_12M 160 >> #define CLK_SCLK_MPHY_IXTAL24 161 >> +#define CLK_SCLK_BPLL 162 >> >> /* gate clocks */ >> #define CLK_UART0 257 >> @@ -195,6 +196,18 @@ >> #define CLK_ACLK432_CAM 518 >> #define CLK_ACLK_FL1550_CAM 519 >> #define CLK_ACLK550_CAM 520 >> +#define CLK_CLKM_PHY0 521 >> +#define CLK_CLKM_PHY1 522 >> +#define CLK_ACLK_PPMU_DREX0_0 523 >> +#define CLK_ACLK_PPMU_DREX0_1 524 >> +#define CLK_ACLK_PPMU_DREX1_0 525 >> +#define CLK_ACLK_PPMU_DREX1_1 526 >> +#define CLK_PCLK_PPMU_DREX0_0 527 >> +#define CLK_PCLK_PPMU_DREX0_1 528 >> +#define CLK_PCLK_PPMU_DREX1_0 529 >> +#define CLK_PCLK_PPMU_DREX1_1 530 >> +#define CLK_CDREX_PAUSE 531 >> +#define CLK_CDREX_TIMING_SET 532 > > I cannot find the usage code of both CLK_CDREX_PAUSE > and CLK_CDREX_TIMING_SET in these patchset. Thank you for this catch. I will remove them. Regards, Lukasz > > Please remove them. > > (snip) >