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[209.132.180.67]) by mx.google.com with ESMTP id j10si44295749plb.346.2019.05.02.06.53.40; Thu, 02 May 2019 06:53:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726503AbfEBMc3 (ORCPT + 99 others); Thu, 2 May 2019 08:32:29 -0400 Received: from andre.telenet-ops.be ([195.130.132.53]:37692 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726439AbfEBMc2 (ORCPT ); Thu, 2 May 2019 08:32:28 -0400 Received: from ramsan ([84.194.111.163]) by andre.telenet-ops.be with bizsmtp id 7QYP200023XaVaC01QYPMH; Thu, 02 May 2019 14:32:26 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1hMAsw-0007e7-Vi; Thu, 02 May 2019 14:32:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1hMAsw-0000nj-UF; Thu, 02 May 2019 14:32:22 +0200 From: Geert Uytterhoeven To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Simon Horman , Magnus Damm , Chris Brandt Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 5/5] ARM: dts: rskrza1: Add input switches Date: Thu, 2 May 2019 14:32:20 +0200 Message-Id: <20190502123220.3016-6-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190502123220.3016-1-geert+renesas@glider.be> References: <20190502123220.3016-1-geert+renesas@glider.be> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for input switches SW1-3 on the Renesas RZ/A1 RSK+RZA1 development board. Note that this uses the IRQ interrupts, as the RZ/A1 GPIO controller does not include interrupt support. Signed-off-by: Geert Uytterhoeven --- v3: - No changes, v2: - No changes, v1: - Use rza1-irqc instead of gic. v0: - Sent as an RFC in a reply to another thread. --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 38 ++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index ff24301dc1be54de..99acfe4fe11aaed9 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r7s72100.dtsi" #include +#include #include / { @@ -28,6 +29,37 @@ reg = <0x08000000 0x02000000>; }; + keyboard { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + + key-1 { + interrupt-parent = <&irqc>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "SW1"; + wakeup-source; + }; + + key-2 { + interrupt-parent = <&irqc>; + interrupts = <2 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "SW2"; + wakeup-source; + }; + + key-3 { + interrupt-parent = <&irqc>; + interrupts = <5 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + label = "SW3"; + wakeup-source; + }; + }; + lbsc { #address-cells = <1>; #size-cells = <1>; @@ -101,6 +133,12 @@ ; /* RIIC3SDA */ }; + keyboard_pins: keyboard { + pinmux = , /* IRQ3 */ + , /* IRQ2 */ + ; /* IRQ5 */ + }; + /* Serial Console */ scif2_pins: serial2 { pinmux = , /* TxD2 */ -- 2.17.1