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[78.210.255.2]) by smtp.googlemail.com with ESMTPSA id e8sm4779602wrc.96.2019.05.03.13.32.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 13:32:25 -0700 (PDT) Subject: Re: [PATCH 7/7] clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters To: Valentin Schneider , Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Russell King , Will Deacon , Catalin Marinas , Mark Rutland , Wim Van Sebroeck , Guenter Roeck References: <20190408154907.223536-1-marc.zyngier@arm.com> <20190408154907.223536-8-marc.zyngier@arm.com> <2a60a031-1eab-2d5e-89ff-b5d516545eeb@linaro.org> From: Daniel Lezcano Message-ID: Date: Fri, 3 May 2019 22:32:24 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Valentin, On 30/04/2019 17:39, Valentin Schneider wrote: > Hi, > > On 30/04/2019 16:27, Marc Zyngier wrote: > [...] >>>> @@ -372,6 +392,7 @@ static u32 notrace sun50i_a64_read_cntv_tval_el0(void) >>>> DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); >>>> EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); >>>> >>>> +static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0); >>> >>> Wouldn't make sense to READ_ONCE / WRITE_ONCE instead of using an atomic? >> >> I don't think *_ONCE says anything about the atomicity of the access. It >> only instruct the compiler that this should only be accessed once, and >> not reloaded/rewritten. > > FWIW 7bd3e239d6c6 ("locking: Remove atomicy checks from {READ,WRITE}_ONCE") > points this out. Interesting, thanks for the pointer. -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog