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[78.210.255.2]) by smtp.googlemail.com with ESMTPSA id i30sm4225043wrc.8.2019.05.03.13.31.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 13:31:43 -0700 (PDT) Subject: Re: [PATCH 7/7] clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters To: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Russell King , Will Deacon , Catalin Marinas , Mark Rutland , Wim Van Sebroeck , Guenter Roeck , Valentin Schneider References: <20190408154907.223536-1-marc.zyngier@arm.com> <20190408154907.223536-8-marc.zyngier@arm.com> <2a60a031-1eab-2d5e-89ff-b5d516545eeb@linaro.org> From: Daniel Lezcano Message-ID: <2f3417f6-95e5-f27a-693d-5aa460fb152d@linaro.org> Date: Fri, 3 May 2019 22:31:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On 30/04/2019 17:27, Marc Zyngier wrote: > On 15/04/2019 13:16, Daniel Lezcano wrote: >> On 08/04/2019 17:49, Marc Zyngier wrote: >>> Instead of always going via arch_counter_get_cntvct_stable to >>> access the counter workaround, let's have arch_timer_read_counter >>> to point to the right method. >>> >>> For that, we need to track whether any CPU in the system has a >>> workaround for the counter. This is done by having an atomic >>> variable tracking this. >>> >>> Signed-off-by: Marc Zyngier >>> --- >> >> [ ... ] >> >>> + >>> /* >>> * Default to cp15 based access because arm64 uses this function for >>> * sched_clock() before DT is probed and the cp15 method is guaranteed >>> @@ -372,6 +392,7 @@ static u32 notrace sun50i_a64_read_cntv_tval_el0(void) >>> DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); >>> EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); >>> >>> +static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0); >> >> Wouldn't make sense to READ_ONCE / WRITE_ONCE instead of using an atomic? > > I don't think *_ONCE says anything about the atomicity of the access. It > only instruct the compiler that this should only be accessed once, and > not reloaded/rewritten. In this case, WRITE_ONCE() would work just as > well, but I feel that setting the expectations do matter. > > I also had a vague idea to use this as a refcount to drop the > workarounds as CPUs get hotplugged off, in which case we'd need the RMW > operations to be atomic. > > Anyway, I'm not hell bent on this. If you fundamentally disagree with me > I'll change it. As you are planning to extend its usage for refcounting in the hotplug path, I think it is fine. Thanks -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog