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From:   Paul Cercueil <paul@crapouillou.net>
To:     Ralf Baechle <ralf@linux-mips.org>,
        Paul Burton <paul.burton@mips.com>,
        James Hogan <jhogan@kernel.org>
Cc:     od@zcrc.me, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org, Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH] MIPS: jz4740: Fix Ingenic SoCs sometimes reporting wrong ISA
Date:   Tue,  7 May 2019 21:41:01 +0200
Message-Id: <20190507194101.17112-1-paul@crapouillou.net>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

The config0 register in the Xburst always reports a MIPS32r2
ISA, but not all of them support it.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 arch/mips/jz4740/setup.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
index 7e63c54eb8d2..2508c026bdfa 100644
--- a/arch/mips/jz4740/setup.c
+++ b/arch/mips/jz4740/setup.c
@@ -64,6 +64,7 @@ static unsigned long __init get_board_mach_type(const void *fdt)
 
 void __init plat_mem_setup(void)
 {
+	struct cpuinfo_mips *c = &current_cpu_data;
 	int offset;
 	void *dtb;
 
@@ -81,6 +82,18 @@ void __init plat_mem_setup(void)
 		jz4740_detect_mem();
 
 	mips_machtype = get_board_mach_type(dtb);
+
+	switch (mips_machtype) {
+	case MACH_INGENIC_JZ4740:
+		/*
+		 * The config0 register in the Xburst always reports a MIPS32r2
+		 * ISA, but not all of them support it.
+		 */
+		c->isa_level &= ~MIPS_CPU_ISA_M32R2;
+		break;
+	default:
+		break;
+	}
 }
 
 void __init device_tree_init(void)
-- 
2.21.0.593.g511ec345e18