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From:   Paul Burton <paul.burton@mips.com>
To:     Paul Cercueil <paul@crapouillou.net>
CC:     Ralf Baechle <ralf@linux-mips.org>,
        James Hogan <jhogan@kernel.org>, "od@zcrc.me" <od@zcrc.me>,
        "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] MIPS: jz4740: Fix Ingenic SoCs sometimes reporting wrong
 ISA
Thread-Topic: [PATCH] MIPS: jz4740: Fix Ingenic SoCs sometimes reporting wrong
 ISA
Thread-Index: AQHVBQzWtgDHX7GlGUuN4Nf63DDbiaZgKeoA
Date:   Tue, 7 May 2019 21:15:36 +0000
Message-ID: <20190507211534.ndtngk273ejrvfd2@pburton-laptop>
References: <20190507194101.17112-1-paul@crapouillou.net>
In-Reply-To: <20190507194101.17112-1-paul@crapouillou.net>
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Hi Paul,

On Tue, May 07, 2019 at 09:41:01PM +0200, Paul Cercueil wrote:
> The config0 register in the Xburst always reports a MIPS32r2
> ISA, but not all of them support it.
>=20
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>  arch/mips/jz4740/setup.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>=20
> diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
> index 7e63c54eb8d2..2508c026bdfa 100644
> --- a/arch/mips/jz4740/setup.c
> +++ b/arch/mips/jz4740/setup.c
> @@ -64,6 +64,7 @@ static unsigned long __init get_board_mach_type(const v=
oid *fdt)
> =20
>  void __init plat_mem_setup(void)
>  {
> +	struct cpuinfo_mips *c =3D &current_cpu_data;
>  	int offset;
>  	void *dtb;
> =20
> @@ -81,6 +82,18 @@ void __init plat_mem_setup(void)
>  		jz4740_detect_mem();
> =20
>  	mips_machtype =3D get_board_mach_type(dtb);
> +
> +	switch (mips_machtype) {
> +	case MACH_INGENIC_JZ4740:
> +		/*
> +		 * The config0 register in the Xburst always reports a MIPS32r2
> +		 * ISA, but not all of them support it.
> +		 */
> +		c->isa_level &=3D ~MIPS_CPU_ISA_M32R2;
> +		break;
> +	default:
> +		break;
> +	}
>  }
> =20
>  void __init device_tree_init(void)
> --=20
> 2.21.0.593.g511ec345e18

Would it work to check the PRID instead? That way we could keep the CPU
probing in cpu-probe.c, for example something like this in
cpu_probe_ingenic():

  if ((c->processor_id & PRID_COMP_MASK) =3D=3D PRID_COMP_INGENIC_D0)
    c->isa_level &=3D ~MIPS_CPU_ISA_M32R2;

That relies on the D0 PRID always being MIPS32r1 & other PRIDs always
being MIPS32r2 though - do you know whether that's the case? Our
comments in asm/cpu.h mapping the various PRIDs to SoCs suggests this
would be OK to me.

Thanks,
    Paul