Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp4274150yba; Tue, 7 May 2019 15:23:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqyvaFBaY3w3uqbg0nb37cqthU+MmG8SlURsdQPNFK4Vqi5buHjOHhXwVp4s0rz6ET8VP1AH X-Received: by 2002:a63:7d03:: with SMTP id y3mr41390223pgc.8.1557267804813; Tue, 07 May 2019 15:23:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557267804; cv=none; d=google.com; s=arc-20160816; b=NKic+yZkAfnZd+TK9UHlndLnxzcKMLrnfmxZ8gC2Qa1h4NnRVfkIwYmJ8VAXYv5npC jDzYOZm9Gf2u0BK0Vha96/eyXFBl6Or3xUT23LGpG7JxLGKvT/vXKeSZPeT/bXnPaiFn OSZjVxE16u9iLbG85uOT4jzxMowbal96ibxpDefBVi5c+KdhgeiExPe3VBbzhd+5RXkf GqUz5NN+Z8TSJPlKCrRJKF8LnUgcSn0iLSa3I2HgGyMfCuifLzQ3FGlkVY6JVA1O0Mpp OMhn106R3rnhmVtRfJJqBWu5Fuh5qt61RRMZO8WfFWh1T1PISbibFpF4sqUnGgong0yr 4hhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:dkim-signature; bh=kG2WwpyR7pHycbjDjCi479hB08AsdI45LDcaIB/Ay64=; b=Zkxms9v50PVqdWukNlMh466D6dEwGCnLszmmnYGdZMWrRWu3ROA3MOgbzt+oZqPrPf WQPY9fsRqvsoI3ZZA+KSv+/42C5Ipls9ClK7CH5R/qUz6srcziJTWwlLd57OCaH8IkNh Nrh77uCny1S41c28AmVZ91h0HIfpMY+b6e0bVFAFfgCey2UOS4r7cqSMDnkU0tij6NMb yc8uD4VjrZGk54gE1t72w5a9Gc7k0IsDccHXZUimfG6sDpRzMUhB6LS5UDlesvTEOYt5 1+BZBHAZpc9YWDxZVvrJaXRQwunlffZwCXtWBZ3oWg5ikkn88RPaEPCjrktXLxeUZxPO AYPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@verdurent-com.20150623.gappssmtp.com header.s=20150623 header.b=hjN9Yj59; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d21si20586963pgh.255.2019.05.07.15.23.09; Tue, 07 May 2019 15:23:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@verdurent-com.20150623.gappssmtp.com header.s=20150623 header.b=hjN9Yj59; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726496AbfEGWUy (ORCPT + 99 others); Tue, 7 May 2019 18:20:54 -0400 Received: from mail-ua1-f67.google.com ([209.85.222.67]:39264 "EHLO mail-ua1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726276AbfEGWUx (ORCPT ); Tue, 7 May 2019 18:20:53 -0400 Received: by mail-ua1-f67.google.com with SMTP id v7so4341909ual.6 for ; Tue, 07 May 2019 15:20:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=verdurent-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=kG2WwpyR7pHycbjDjCi479hB08AsdI45LDcaIB/Ay64=; b=hjN9Yj59LATp2bF3ohozr0h4VitiflbvzeOSSbSaBGOTZncsE7cab9AvJ68MTAf1J8 AigRqhDNeiAuuGqitKYp/2M77PEINn2xOVFTboK++LZvbxCTNMTYZgwMBtdOQm1X1eG9 4C6IMmkj2+4bQd5SP+0N/ZyMHWP9b86jy3rIH84FOb0vMCDIA5WZ+ndL74A0c9bAQ2SA 9kccjisOJ6osEzEdxaxcxA4iQGkx/X2L6heAONlMtlyU766jXtqbhtoUE5Pi5AAA9ElW 36e/N46YOH+pvb322fsrB0QNHmsFDi9PWJLbt4DYxsh+kDAH5JHvq+c0F5rGJgHMD087 Vwnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=kG2WwpyR7pHycbjDjCi479hB08AsdI45LDcaIB/Ay64=; b=EXTu0Jc8/cmdryLilG4J9m4JzZYmeiFKQ2ZhrtOUVdMj3tLEI1NkLGF1Snk43tytoP Ob32TD0u7k+d+P3FHzQnen/VX1dW7yZge0HycGej1pFfM+eoq3ImyhjBarbaGTy25fcx d6sFnWpmS4CDfxNVIQxWc+B1mZmmOEIB8CSoYkwxzG2DDcR8NsAM6ZX5v2Uq3sBXSui0 m6+6vfM/LevDYuBnU2VoCgBJlrzqFOBQAOZWwtjHm8qaW4IBFfOIa8GeL3jo70Lg1U/d MxaMh9wFFkdtQyYxTobNPuXVr2yt+JHisNlxQ1KASkkf+XNf16a/yqs75xduLgdCemot iIaQ== X-Gm-Message-State: APjAAAUxBDi7f3JOBS+QMiCus5jlBX5tgBhnH9pz5UJjOlJqSCNS4+R+ aE6Gqdq2CUBHH6XL4NVbeQrPhNQd1q1onvnWxJXNZA== X-Received: by 2002:ab0:70d4:: with SMTP id r20mr16052105ual.67.1557267652335; Tue, 07 May 2019 15:20:52 -0700 (PDT) MIME-Version: 1.0 References: <1540920209-28954-1-git-send-email-rplsssn@codeaurora.org> In-Reply-To: <1540920209-28954-1-git-send-email-rplsssn@codeaurora.org> From: Amit Kucheria Date: Wed, 8 May 2019 03:50:40 +0530 Message-ID: Subject: Re: [PATCH v2] arm64: dts: sdm845: Add PSCI cpuidle low power states To: "Raju P.L.S.S.S.N" Cc: Andy Gross , David Brown , linux-arm-msm , "open list:ARM/QUALCOMM SUPPORT" , Rajendra Nayak , Bjorn Andersson , LKML , Linux PM list , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Stephen Boyd , evgreen@chromium.org, Douglas Anderson , Matthias Kaehlcke , ilina@codeaurora.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 30, 2018 at 10:53 PM Raju P.L.S.S.S.N wrote: > > Add device bindings for cpuidle states for cpu devices. Raju: Did this patch fall through the cracks? It would be nice to land this while Lina works on setting up the infrastructure to do hierarchical power domains. > Cc: > Signed-off-by: Raju P.L.S.S.S.N > --- > Changes in v2 > - Address comments from Doug > --- > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 62 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 0c9a2aa..3a8381e 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -96,6 +96,7 @@ > reg = <0x0 0x0>; > enable-method = "psci"; > next-level-cache = <&L2_0>; > + cpu-idle-states = <&C0_CPU_PD &C0_CPU_RPD &CLUSTER_PD>; May I suggest using more generic names here instead of C0_CPU_PD and move the QC-specific description to the idle-state-name property? C0 and C4 isn't easy to understand at a glance. Neither is PD and RPD. Something like big_cpu_retention, big_cpu_sleep, little_cpu_retention, little_cpu_sleep, cluster_sleep? Or big_cpu_idle_0, big_cpu_idle_1, big_cpu_idle_2 for states with increasing breakeven times. I've commented below on what it might look like. > L2_0: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -111,6 +112,7 @@ > reg = <0x0 0x100>; > enable-method = "psci"; > next-level-cache = <&L2_100>; > + cpu-idle-states = <&C0_CPU_PD &C0_CPU_RPD &CLUSTER_PD>; > L2_100: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -123,6 +125,7 @@ > reg = <0x0 0x200>; > enable-method = "psci"; > next-level-cache = <&L2_200>; > + cpu-idle-states = <&C0_CPU_PD &C0_CPU_RPD &CLUSTER_PD>; > L2_200: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -135,6 +138,7 @@ > reg = <0x0 0x300>; > enable-method = "psci"; > next-level-cache = <&L2_300>; > + cpu-idle-states = <&C0_CPU_PD &C0_CPU_RPD &CLUSTER_PD>; > L2_300: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -147,6 +151,7 @@ > reg = <0x0 0x400>; > enable-method = "psci"; > next-level-cache = <&L2_400>; > + cpu-idle-states = <&C4_CPU_PD &C4_CPU_RPD &CLUSTER_PD>; > L2_400: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -159,6 +164,7 @@ > reg = <0x0 0x500>; > enable-method = "psci"; > next-level-cache = <&L2_500>; > + cpu-idle-states = <&C4_CPU_PD &C4_CPU_RPD &CLUSTER_PD>; > L2_500: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -171,6 +177,7 @@ > reg = <0x0 0x600>; > enable-method = "psci"; > next-level-cache = <&L2_600>; > + cpu-idle-states = <&C4_CPU_PD &C4_CPU_RPD &CLUSTER_PD>; > L2_600: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > @@ -183,11 +190,66 @@ > reg = <0x0 0x700>; > enable-method = "psci"; > next-level-cache = <&L2_700>; > + cpu-idle-states = <&C4_CPU_PD &C4_CPU_RPD &CLUSTER_PD>; > L2_700: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > }; > }; > + > + idle-states { > + entry-method = "psci"; > + > + C0_CPU_PD: c0-power-down { big_cpu_retention: big-cpu-retention > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x40000003>; > + entry-latency-us = <350>; > + exit-latency-us = <461>; > + min-residency-us = <1890>; > + local-timer-stop; > + idle-state-name = "power-down"; "big-cpu-power-down" > + }; > + > + C0_CPU_RPD: c0-rail-power-down { big_cpu_sleep: big-cpu-sleep > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x40000004>; > + entry-latency-us = <360>; > + exit-latency-us = <531>; > + min-residency-us = <3934>; > + local-timer-stop; > + idle-state-name = "rail-power-down"; "big-cpu-rail-power-down" > + }; > + > + C4_CPU_PD: c4-power-down { little_cpu_retention: little-cpu-retention > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x40000003>; > + entry-latency-us = <264>; > + exit-latency-us = <621>; > + min-residency-us = <952>; > + local-timer-stop; > + idle-state-name = "power-down"; "little-cpu-power-down" and so and so forth. You get the idea. > + }; > + > + C4_CPU_RPD: c4-rail-power-down { > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x40000004>; > + entry-latency-us = <702>; > + exit-latency-us = <1061>; > + min-residency-us = <4488>; > + local-timer-stop; > + idle-state-name = "rail-power-down"; > + }; > + > + CLUSTER_PD: cluster-power-down { > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x400000F4>; > + entry-latency-us = <3263>; > + exit-latency-us = <6562>; > + min-residency-us = <9987>; > + local-timer-stop; > + idle-state-name = "cluster-power-down"; > + }; > + }; > }; > > pmu { > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of the Code Aurora Forum, hosted by The Linux Foundation. >