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From:   Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To:     p.zabel@pengutronix.de, robh+dt@kernel.org
Cc:     linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        haitao.suo@bitmain.com, darren.tsao@bitmain.com,
        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v2 1/4] dt-bindings: reset: Add devicetree binding for BM1880 reset controller
Date:   Wed,  8 May 2019 22:23:16 +0530
Message-Id: <20190508165319.19822-2-manivannan.sadhasivam@linaro.org>
In-Reply-To: <20190508165319.19822-1-manivannan.sadhasivam@linaro.org>
References: <20190508165319.19822-1-manivannan.sadhasivam@linaro.org>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Add devicetree binding for Bitmain BM1880 SoC reset controller. This SoC
has two reset controllers each controlling reset lines of different
peripherals.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../bindings/reset/bitmain,bm1880-reset.txt   |  18 +++
 .../dt-bindings/reset/bitmain,bm1880-reset.h  | 106 ++++++++++++++++++
 2 files changed, 124 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt
 create mode 100644 include/dt-bindings/reset/bitmain,bm1880-reset.h

diff --git a/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt b/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt
new file mode 100644
index 000000000000..0674ae904b19
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/bitmain,bm1880-reset.txt
@@ -0,0 +1,18 @@
+Bitmain BM1880 SoC Reset Controller
+===================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible:   Should be "bitmain,bm1880-reset"
+- reg:          Offset and length of reset controller space in SCTRL.
+- #reset-cells: Must be 1.
+
+Example:
+
+        reset: reset-controller@800 {
+                compatible = "bitmain,bm1880-reset";
+                reg = <0x800 0x8>;
+                #reset-cells = <1>;
+        };
diff --git a/include/dt-bindings/reset/bitmain,bm1880-reset.h b/include/dt-bindings/reset/bitmain,bm1880-reset.h
new file mode 100644
index 000000000000..e8103ce6f4d6
--- /dev/null
+++ b/include/dt-bindings/reset/bitmain,bm1880-reset.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Bitmain Ltd.
+ * Copyright (c) 2019 Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_BM1880_RESET_H
+#define _DT_BINDINGS_BM1880_RESET_H
+
+#define BM1880_RST_MAIN_AP		0
+#define BM1880_RST_SECOND_AP		1
+#define BM1880_RST_DDR			2
+#define BM1880_RST_VIDEO		3
+#define BM1880_RST_JPEG			4
+#define BM1880_RST_VPP			5
+#define BM1880_RST_GDMA			6
+#define BM1880_RST_AXI_SRAM		7
+#define BM1880_RST_TPU			8
+#define BM1880_RST_USB			9
+#define BM1880_RST_ETH0			10
+#define BM1880_RST_ETH1			11
+#define BM1880_RST_NAND			12
+#define BM1880_RST_EMMC			13
+#define BM1880_RST_SD			14
+#define BM1880_RST_SDMA			15
+#define BM1880_RST_I2S0			16
+#define BM1880_RST_I2S1			17
+#define BM1880_RST_UART0_1_CLK		18
+#define BM1880_RST_UART0_1_ACLK		19
+#define BM1880_RST_UART2_3_CLK		20
+#define BM1880_RST_UART2_3_ACLK		21
+#define BM1880_RST_MINER		22
+#define BM1880_RST_I2C0			23
+#define BM1880_RST_I2C1			24
+#define BM1880_RST_I2C2			25
+#define BM1880_RST_I2C3			26
+#define BM1880_RST_I2C4			27
+#define BM1880_RST_PWM0			28
+#define BM1880_RST_PWM1			29
+#define BM1880_RST_PWM2			30
+#define BM1880_RST_PWM3			31
+#define BM1880_RST_SPI			32
+#define BM1880_RST_GPIO0		33
+#define BM1880_RST_GPIO1		34
+#define BM1880_RST_GPIO2		35
+#define BM1880_RST_EFUSE		36
+#define BM1880_RST_WDT			37
+#define BM1880_RST_AHB_ROM		38
+#define BM1880_RST_SPIC			39
+
+#define BM1880_CLK_RST_A53		0
+#define BM1880_CLK_RST_50M_A53		1
+#define BM1880_CLK_RST_AHB_ROM		2
+#define BM1880_CLK_RST_AXI_SRAM		3
+#define BM1880_CLK_RST_DDR_AXI		4
+#define BM1880_CLK_RST_EFUSE		5
+#define BM1880_CLK_RST_APB_EFUSE	6
+#define BM1880_CLK_RST_AXI_EMMC		7
+#define BM1880_CLK_RST_EMMC		8
+#define BM1880_CLK_RST_100K_EMMC	9
+#define BM1880_CLK_RST_AXI_SD		10
+#define BM1880_CLK_RST_SD		11
+#define BM1880_CLK_RST_100K_SD		12
+#define BM1880_CLK_RST_500M_ETH0	13
+#define BM1880_CLK_RST_AXI_ETH0		14
+#define BM1880_CLK_RST_500M_ETH1	15
+#define BM1880_CLK_RST_AXI_ETH1		16
+#define BM1880_CLK_RST_AXI_GDMA		17
+#define BM1880_CLK_RST_APB_GPIO		18
+#define BM1880_CLK_RST_APB_GPIO_INTR	19
+#define BM1880_CLK_RST_GPIO_DB		20
+#define BM1880_CLK_RST_AXI_MINER	21
+#define BM1880_CLK_RST_AHB_SF		22
+#define BM1880_CLK_RST_SDMA_AXI		23
+#define BM1880_CLK_RST_SDMA_AUD		24
+#define BM1880_CLK_RST_APB_I2C		25
+#define BM1880_CLK_RST_APB_WDT		26
+#define BM1880_CLK_RST_APB_JPEG		27
+#define BM1880_CLK_RST_JPEG_AXI		28
+#define BM1880_CLK_RST_AXI_NF		29
+#define BM1880_CLK_RST_APB_NF		30
+#define BM1880_CLK_RST_NF		31
+#define BM1880_CLK_RST_APB_PWM		32
+#define BM1880_CLK_RST_RV		33
+#define BM1880_CLK_RST_APB_SPI		34
+#define BM1880_CLK_RST_TPU_AXI		35
+#define BM1880_CLK_RST_UART_500M	36
+#define BM1880_CLK_RST_APB_UART		37
+#define BM1880_CLK_RST_APB_I2S		38
+#define BM1880_CLK_RST_AXI_USB		39
+#define BM1880_CLK_RST_APB_USB		40
+#define BM1880_CLK_RST_125M_USB		41
+#define BM1880_CLK_RST_33K_USB		42
+#define BM1880_CLK_RST_12M_USB		43
+#define BM1880_CLK_RST_APB_VIDEO	44
+#define BM1880_CLK_RST_VIDEO_AXI	45
+#define BM1880_CLK_RST_VPP_AXI		46
+#define BM1880_CLK_RST_APB_VPP		47
+#define BM1880_CLK_RST_AXI1		48
+#define BM1880_CLK_RST_AXI2		49
+#define BM1880_CLK_RST_AXI3		50
+#define BM1880_CLK_RST_AXI4		51
+#define BM1880_CLK_RST_AXI5		52
+#define BM1880_CLK_RST_AXI6		53
+
+#endif /* _DT_BINDINGS_BM1880_RESET_H */
-- 
2.17.1