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[209.132.180.67]) by mx.google.com with ESMTP id 70si6391258plc.88.2019.05.10.04.48.36; Fri, 10 May 2019 04:48:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@verdurent-com.20150623.gappssmtp.com header.s=20150623 header.b=bmS478xn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727582AbfEJLcs (ORCPT + 99 others); Fri, 10 May 2019 07:32:48 -0400 Received: from mail-vs1-f65.google.com ([209.85.217.65]:37359 "EHLO mail-vs1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727548AbfEJLcq (ORCPT ); Fri, 10 May 2019 07:32:46 -0400 Received: by mail-vs1-f65.google.com with SMTP id w13so3430765vsc.4 for ; Fri, 10 May 2019 04:32:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=verdurent-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=yZ6jdrso6YQALlBTVPqF+EIbIXa/5T6qU7atBIjlHzE=; b=bmS478xntfqH8sBnIfU0e8lUZ+IyJrNyjuKlvqHnRfKi6EW1w+GTj1v0vKCz9XqnLZ Ax6dlcJJbw5ZhA8Z5+9m9quq8smi7gN/io/ZBbW1VJE4d1IT1bLeDwRcQqddIOnly++7 UDaesyMK53z6umFQeMQkjirZAR+wjSjy99YnOX5tqgXEQrxi0oEirU6tP+xVqiizrhhz +fFIDs+wo6aeCxRnu/g7weKH26jovcsH1/xDu9FLyiUPhlQe1XtOGHpJjeKXRegCkojD woBhUloWtO9g9l+vRs3YDmAiegrNq1IECF81rc7nMc3gn6gG/G4BCTtE+hDoVU32rJ4q +1lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yZ6jdrso6YQALlBTVPqF+EIbIXa/5T6qU7atBIjlHzE=; b=a8VsJGVITTjfOhZwgT16tqwg0bbyUEfzW26Js8pYxcBZWozwCLDBkb2E2hlL1rjcjE UrRO8nac3BrC5vk9ke2zzTuGLFUTond2dE3iUMcmPXgovCFe54tCxj5uqW9FxHguaNQg w/7XhlZRWArbSzQKJhBnP0XykuDUEFUA32aNcQ+0SQgigSpT8ifr1xra2dqCgLFBanig u1RHOYRKFFbXV2aIr3F57tW86AVN3oN2hFv7zgwrHlx5UCyBI4znYyQBqyBd9u7WEF+U WXQ7v+a0aEDELc6UCMeizhGa/1g1AIl8AnyiCspCpMWmV/HSp0hSN7uu/kwzkQQDvX3p wqJg== X-Gm-Message-State: APjAAAVIsv4OCPWoRZZWxO4d1pHgFSyTQGQKUQsI65djaUpW/o/s7UU3 znvqKLfmx9OxaQpvQcnSKagocL/Ka3Ii59krCKWD0A== X-Received: by 2002:a67:ad03:: with SMTP id t3mr4940787vsl.159.1557487965449; Fri, 10 May 2019 04:32:45 -0700 (PDT) MIME-Version: 1.0 References: <1540920209-28954-1-git-send-email-rplsssn@codeaurora.org> In-Reply-To: From: Amit Kucheria Date: Fri, 10 May 2019 17:02:34 +0530 Message-ID: Subject: Re: [PATCH v2] arm64: dts: sdm845: Add PSCI cpuidle low power states To: "Raju P.L.S.S.S.N" , mkshah@codeaurora.org Cc: Andy Gross , David Brown , linux-arm-msm , "open list:ARM/QUALCOMM SUPPORT" , Rajendra Nayak , Bjorn Andersson , LKML , Linux PM list , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Stephen Boyd , evgreen@chromium.org, Douglas Anderson , Matthias Kaehlcke , ilina@codeaurora.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 8, 2019 at 3:50 AM Amit Kucheria wrote: > > On Tue, Oct 30, 2018 at 10:53 PM Raju P.L.S.S.S.N > wrote: > > > > Add device bindings for cpuidle states for cpu devices. > > Raju: Did this patch fall through the cracks? It would be nice to land > this while Lina works on setting up the infrastructure to do > hierarchical power domains. After talking offline with Raju, I've added this patch with some cleanups to my qcom cpuidle series. > > Cc: > > Signed-off-by: Raju P.L.S.S.S.N > > --- > > Changes in v2 > > - Address comments from Doug > > --- > > --- > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 62 ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 62 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > index 0c9a2aa..3a8381e 100644 > > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > > @@ -96,6 +96,7 @@ > > reg = <0x0 0x0>; > > enable-method = "psci"; > > next-level-cache = <&L2_0>; > > + cpu-idle-states = <&C0_CPU_PD &C0_CPU_RPD &CLUSTER_PD>; > > May I suggest using more generic names here instead of C0_CPU_PD and > move the QC-specific description to the idle-state-name property? C0 > and C4 isn't easy to understand at a glance. Neither is PD and RPD. > > Something like big_cpu_retention, big_cpu_sleep, little_cpu_retention, > little_cpu_sleep, cluster_sleep? > Or big_cpu_idle_0, big_cpu_idle_1, big_cpu_idle_2 for states with > increasing breakeven times. > > I've commented below on what it might look like. > > > L2_0: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -111,6 +112,7 @@ > > reg = <0x0 0x100>; > > enable-method = "psci"; > > next-level-cache = <&L2_100>; > > + cpu-idle-states = <&C0_CPU_PD &C0_CPU_RPD &CLUSTER_PD>; > > L2_100: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -123,6 +125,7 @@ > > reg = <0x0 0x200>; > > enable-method = "psci"; > > next-level-cache = <&L2_200>; > > + cpu-idle-states = <&C0_CPU_PD &C0_CPU_RPD &CLUSTER_PD>; > > L2_200: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -135,6 +138,7 @@ > > reg = <0x0 0x300>; > > enable-method = "psci"; > > next-level-cache = <&L2_300>; > > + cpu-idle-states = <&C0_CPU_PD &C0_CPU_RPD &CLUSTER_PD>; > > L2_300: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -147,6 +151,7 @@ > > reg = <0x0 0x400>; > > enable-method = "psci"; > > next-level-cache = <&L2_400>; > > + cpu-idle-states = <&C4_CPU_PD &C4_CPU_RPD &CLUSTER_PD>; > > L2_400: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -159,6 +164,7 @@ > > reg = <0x0 0x500>; > > enable-method = "psci"; > > next-level-cache = <&L2_500>; > > + cpu-idle-states = <&C4_CPU_PD &C4_CPU_RPD &CLUSTER_PD>; > > L2_500: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -171,6 +177,7 @@ > > reg = <0x0 0x600>; > > enable-method = "psci"; > > next-level-cache = <&L2_600>; > > + cpu-idle-states = <&C4_CPU_PD &C4_CPU_RPD &CLUSTER_PD>; > > L2_600: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > @@ -183,11 +190,66 @@ > > reg = <0x0 0x700>; > > enable-method = "psci"; > > next-level-cache = <&L2_700>; > > + cpu-idle-states = <&C4_CPU_PD &C4_CPU_RPD &CLUSTER_PD>; > > L2_700: l2-cache { > > compatible = "cache"; > > next-level-cache = <&L3_0>; > > }; > > }; > > + > > + idle-states { > > + entry-method = "psci"; > > + > > + C0_CPU_PD: c0-power-down { > > big_cpu_retention: big-cpu-retention > > > + compatible = "arm,idle-state"; > > + arm,psci-suspend-param = <0x40000003>; > > + entry-latency-us = <350>; > > + exit-latency-us = <461>; > > + min-residency-us = <1890>; > > + local-timer-stop; > > + idle-state-name = "power-down"; > > "big-cpu-power-down" > > > + }; > > + > > + C0_CPU_RPD: c0-rail-power-down { > > big_cpu_sleep: big-cpu-sleep > > > + compatible = "arm,idle-state"; > > + arm,psci-suspend-param = <0x40000004>; > > + entry-latency-us = <360>; > > + exit-latency-us = <531>; > > + min-residency-us = <3934>; > > + local-timer-stop; > > + idle-state-name = "rail-power-down"; > > "big-cpu-rail-power-down" > > > + }; > > + > > + C4_CPU_PD: c4-power-down { > > little_cpu_retention: little-cpu-retention > > > + compatible = "arm,idle-state"; > > + arm,psci-suspend-param = <0x40000003>; > > + entry-latency-us = <264>; > > + exit-latency-us = <621>; > > + min-residency-us = <952>; > > + local-timer-stop; > > + idle-state-name = "power-down"; > > "little-cpu-power-down" and so and so forth. You get the idea. > > > + }; > > + > > + C4_CPU_RPD: c4-rail-power-down { > > + compatible = "arm,idle-state"; > > + arm,psci-suspend-param = <0x40000004>; > > + entry-latency-us = <702>; > > + exit-latency-us = <1061>; > > + min-residency-us = <4488>; > > + local-timer-stop; > > + idle-state-name = "rail-power-down"; > > + }; > > + > > + CLUSTER_PD: cluster-power-down { > > + compatible = "arm,idle-state"; > > + arm,psci-suspend-param = <0x400000F4>; > > + entry-latency-us = <3263>; > > + exit-latency-us = <6562>; > > + min-residency-us = <9987>; > > + local-timer-stop; > > + idle-state-name = "cluster-power-down"; > > + }; > > + }; > > }; > > > > pmu { > > -- > > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > > of the Code Aurora Forum, hosted by The Linux Foundation. > >