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[209.132.180.67]) by mx.google.com with ESMTP id m5si8942618pgt.73.2019.05.10.15.42.06; Fri, 10 May 2019 15:42:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=2BQZd867; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728169AbfEJWke (ORCPT + 99 others); Fri, 10 May 2019 18:40:34 -0400 Received: from mail.kernel.org ([198.145.29.99]:47894 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726986AbfEJWkd (ORCPT ); Fri, 10 May 2019 18:40:33 -0400 Received: from mail-qk1-f175.google.com (mail-qk1-f175.google.com [209.85.222.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A45FB217D6; Fri, 10 May 2019 22:40:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557528031; bh=sjg797I3Ege8CH2yMEKO3LN7YMxSK0+Tf/Ul0+K1ZmU=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=2BQZd867VQk7T/6xVDuphNMg8PT5izoOPVjRH879mo5UuHee3+ME5We5UOp8oRApd iNSg0CMTjRLx+00A9EkpzztyQHHRMInm04SGcjFY0N6Ai1ssRwJbeHEvYjgtLq3o/8 Wx03509gNXFgIf1KQaGDcBNEhhyg+soHiT3IF6pM= Received: by mail-qk1-f175.google.com with SMTP id c1so3365531qkk.4; Fri, 10 May 2019 15:40:31 -0700 (PDT) X-Gm-Message-State: APjAAAW4lI9YZcdBQOHTUO12vKApasFtUEa37qKOlUhFHw63XY3DrNho Z4MY0Q3mcIdVCFavI5lHXsb3A24Yv0TtGLIEow== X-Received: by 2002:a37:c42:: with SMTP id 63mr10276099qkm.326.1557528030863; Fri, 10 May 2019 15:40:30 -0700 (PDT) MIME-Version: 1.0 References: <20190507203749.3384-1-ilina@codeaurora.org> <20190507203749.3384-5-ilina@codeaurora.org> In-Reply-To: <20190507203749.3384-5-ilina@codeaurora.org> From: Rob Herring Date: Fri, 10 May 2019 17:40:19 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 04/11] of: irq: document properties for wakeup interrupt parent To: Lina Iyer Cc: Stephen Boyd , Evan Green , Marc Zyngier , Linus Walleij , "linux-kernel@vger.kernel.org" , "Raju P.L.S.S.S.N" , linux-arm-msm , Thierry Reding , Bjorn Andersson , Doug Anderson , devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 7, 2019 at 3:41 PM Lina Iyer wrote: > > Some interrupt controllers in a SoC, are always powered on and have a > select interrupts routed to them, so that they can wakeup the SoC from > suspend. Add wakeup-parent DT property to refer to these interrupt > controllers. > > If the interrupts routed to the wakeup parent are not sequential, than a > map needs to exist to associate the same interrupt line on multiple > interrupt controllers. Providing this map in every driver is cumbersome. > Let's add this in the device tree and document the properties to map the > interrupt specifiers > > Cc: devicetree@vger.kernel.org > Signed-off-by: Lina Iyer > --- > Changes in v5: > - Update documentation to describe masks in the example > Changes in v4: > - Added this documentation > --- > .../interrupt-controller/interrupts.txt | 54 +++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt > index 8a3c40829899..e3e43f5d5566 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt > +++ b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt > @@ -108,3 +108,57 @@ commonly used: > sensitivity = <7>; > }; > }; > + > +3) Interrupt wakeup parent > +-------------------------- > + > +Some interrupt controllers in a SoC, are always powered on and have a select > +interrupts routed to them, so that they can wakeup the SoC from suspend. These > +interrupt controllers do not fall into the category of a parent interrupt > +controller and can be specified by the "wakeup-parent" property and contain a > +single phandle referring to the wakeup capable interrupt controller. > + > + Example: > + wakeup-parent = <&pdc_intc>; > + > + > +4) Interrupt mapping > +-------------------- > + > +Sometimes interrupts may be detected by more than one interrupt controller > +(depending on which controller is active). The interrupt controllers may not > +be in hierarchy and therefore the interrupt controller driver is required to > +establish the relationship between the same interrupt at different interrupt > +controllers. If these interrupts are not sequential then a map needs to be > +specified to help identify these interrupts. > + > +Mapping the interrupt specifiers in the device tree can be done using the > +"irqdomain-map" property. The property contains interrupt specifier at the > +current interrupt controller followed by the interrupt specifier at the mapped > +interrupt controller. > + > + irqdomain-map = I'm wondering why we need a new map property rather than just using interrupt-map? Contrary to what Linus said, it is not PCI only. It would be an extension of the current behavior. It's generally used to map each interrupt to different parents or swizzle the routing (in the PCI case). Generally, a node would be either an 'interrupt-controller' or an 'interrupt-map' node. The interrupt parsing code (for the kernel at least) prioritizes 'interrupt-controller' path, so adding 'interrupt-map' could be done without changing behavior. Another concern I have with this is it only solves the problem of an IRQ routed to multiple parents for the case of 2 parents. What happens when we have an IRQ routed to 3 different parents? Maybe the solution is the incoming-interrupt-specifier can be listed more than once. Marc already expressed concerns with the scalability of interrupt-map property, so that's maybe not an ideal solution. > + > +The optional properties "irqdomain-map-mask" and "irqdomain-map-pass-thru" may > +be provided to help interpret the valid bits of the incoming and mapped > +interrupt specifiers respectively. > + > + Example: > + intc: interrupt-controller@17a00000 { > + #interrupt-cells = <3>; The phandle doesn't count as a cell, so this should be 2. > + }; > + > + pinctrl@3400000 { > + #interrupt-cells = <2>; > + irqdomain-map = <22 0 &intc 36 0>, <24 0 &intc 37 0>; > + irqdomain-map-mask = <0xff 0>; > + irqdomain-map-pass-thru = <0 0xff>; > + }; > + > +In the above example, the input interrupt specifier map-mask <0xff 0> applied > +on the incoming interrupt specifier of the map <22 0>, <24 0>, returns the > +input interrupt 22, 24 etc. The second argument being irq type is immaterial > +from the map and is used from the incoming request instead. The pass-thru > +specifier parses the output interrupt specifier from the rest of the unparsed > +argments from the map <&intc 36 0>, <&intc 37 0> etc to return the output > +interrupt 36, 37 etc. > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >