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[209.132.180.67]) by mx.google.com with ESMTP id e40si5550028plb.180.2019.05.13.19.09.01; Mon, 13 May 2019 19:09:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=AWYLnYQX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726720AbfENCHw (ORCPT + 99 others); Mon, 13 May 2019 22:07:52 -0400 Received: from mail.kernel.org ([198.145.29.99]:43128 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726547AbfENCHv (ORCPT ); Mon, 13 May 2019 22:07:51 -0400 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5F71E21726 for ; Tue, 14 May 2019 02:07:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557799669; bh=194cYzJSEWelAQdAamSQ+HGCjU5m9KnJ95hz0wnBDOw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=AWYLnYQXqecynVt8YdrwsS+Xfe7b6aCvx26D2JOr6eOFfLp34kg8+aoO6xKlIGs+n if+Vo2q8fZoCeysFzcDiUsbbBG2udM5TCiMj02dJ8dNOct9/ZqVispF3WQeOuagvIo NudBGjsk7KLG9PNcK2KUdJ8z3KuRVee+3Ctp2/cA= Received: by mail-wm1-f44.google.com with SMTP id y3so1121504wmm.2 for ; Mon, 13 May 2019 19:07:49 -0700 (PDT) X-Gm-Message-State: APjAAAVjQxWECBaA9K+APa6fDwHZEDZ7NbHDdKO1zBfA4q20k3QgjsBd B2f8LK7Y4gG0rHJGzfrBXsXIxV6NNMRgjenlHPVUJg== X-Received: by 2002:a7b:c844:: with SMTP id c4mr6663648wml.108.1557799667844; Mon, 13 May 2019 19:07:47 -0700 (PDT) MIME-Version: 1.0 References: <1557758315-12667-1-git-send-email-alexandre.chartre@oracle.com> In-Reply-To: From: Andy Lutomirski Date: Mon, 13 May 2019 19:07:36 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC KVM 00/27] KVM Address Space Isolation To: Liran Alon Cc: Andy Lutomirski , Alexandre Chartre , Paolo Bonzini , Radim Krcmar , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Dave Hansen , Peter Zijlstra , kvm list , X86 ML , Linux-MM , LKML , Konrad Rzeszutek Wilk , jan.setjeeilers@oracle.com, Jonathan Adams Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 13, 2019 at 2:09 PM Liran Alon wrote: > > > > > On 13 May 2019, at 21:17, Andy Lutomirski wrote: > > > >> I expect that the KVM address space can eventually be expanded to incl= ude > >> the ioctl syscall entries. By doing so, and also adding the KVM page t= able > >> to the process userland page table (which should be safe to do because= the > >> KVM address space doesn't have any secret), we could potentially handl= e the > >> KVM ioctl without having to switch to the kernel pagetable (thus effec= tively > >> eliminating KPTI for KVM). Then the only overhead would be if a VM-Exi= t has > >> to be handled using the full kernel address space. > >> > > > > In the hopefully common case where a VM exits and then gets re-entered > > without needing to load full page tables, what code actually runs? > > I'm trying to understand when the optimization of not switching is > > actually useful. > > > > Allowing ioctl() without switching to kernel tables sounds... > > extremely complicated. It also makes the dubious assumption that user > > memory contains no secrets. > > Let me attempt to clarify what we were thinking when creating this patch = series: > > 1) It is never safe to execute one hyperthread inside guest while it=E2= =80=99s sibling hyperthread runs in a virtual address space which contains = secrets of host or other guests. > This is because we assume that using some speculative gadget (such as hal= f-Spectrev2 gadget), it will be possible to populate *some* CPU core resour= ce which could then be *somehow* leaked by the hyperthread running inside g= uest. In case of L1TF, this would be data populated to the L1D cache. > > 2) Because of (1), every time a hyperthread runs inside host kernel, we m= ust make sure it=E2=80=99s sibling is not running inside guest. i.e. We mus= t kick the sibling hyperthread outside of guest using IPI. > > 3) From (2), we should have theoretically deduced that for every #VMExit,= there is a need to kick the sibling hyperthread also outside of guest unti= l the #VMExit is completed. Such a patch series was implemented at some poi= nt but it had (obviously) significant performance hit. > > 4) The main goal of this patch series is to preserve (2), but to avoid the overhead specified in (3). > > The way this patch series achieves (4) is by observing that during the ru= n of a VM, most #VMExits can be handled rather quickly and locally inside K= VM and doesn=E2=80=99t need to reference any data that is not relevant to t= his VM or KVM code. Therefore, if we will run these #VMExits in an isolated= virtual address space (i.e. KVM isolated address space), there is no need = to kick the sibling hyperthread from guest while these #VMExits handlers ru= n. Thanks! This clarifies a lot of things. > The hope is that the very vast majority of #VMExit handlers will be able = to completely run without requiring to switch to full address space. Theref= ore, avoiding the performance hit of (2). > However, for the very few #VMExits that does require to run in full kerne= l address space, we must first kick the sibling hyperthread outside of gues= t and only then switch to full kernel address space and only once all hyper= threads return to KVM address space, then allow then to enter into guest. What exactly does "kick" mean in this context? It sounds like you're going to need to be able to kick sibling VMs from extremely atomic contexts like NMI and MCE.