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([2a01:cb1d:379:8b00:1910:6694:7019:d3a]) by smtp.gmail.com with ESMTPSA id u14sm14706822wrn.30.2019.05.14.02.14.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 02:14:53 -0700 (PDT) Subject: Re: [baylibre-upstreaming] [PATCH 0/3] mmc: meson-gx: add ddr-access-quirk support To: baylibre-upstreaming@groups.io, narmstrong@baylibre.com, ulf.hansson@linaro.org, khilman@baylibre.com Cc: linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20190513091548.16674-1-narmstrong@baylibre.com> From: guillaume La Roque Message-ID: <65423579-52c0-40ca-143a-6bc6ed33c90e@baylibre.com> Date: Tue, 14 May 2019 11:14:53 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190513091548.16674-1-narmstrong@baylibre.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/13/19 11:15 AM, Neil Armstrong wrote: > On the Amlogic G12A SoC family, (only) the SDIO controller fails to access > the data from DDR, leading to a broken controller. > > Add the amlogic,ddr-access-quirk property so signal this particular > controller has this bug and needs a quirk to work properly. > > But each MMC controller has 1,5KiB of SRAM after the registers, that can > be used as bounce buffer to avoid direct DDR access from the integrated > DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized). > > The quirk is to disable the chained descriptor for this controller, and > use this SRAM memory zone as buffer for the bounce buffer fallback mode. > > The performance hit hasn't been evaluated, but the fix has been tested > using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave > 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed > at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock. > > Neil Armstrong (3): > dt-bindings: mmc: meson-gx: add ddr-access-quirk property > mmc: meson-gx: add ddr-access-quirk > arm64: dts: meson-g12a: add ddr-access-quirk property to SDIO > controller > > .../bindings/mmc/amlogic,meson-gx.txt | 4 ++ > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + > drivers/mmc/host/meson-gx-mmc.c | 65 +++++++++++++++---- > 3 files changed, 57 insertions(+), 13 deletions(-) > Test with SEI510 board no problem or regression seen Tested-by: Guillaume La Roque