Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp6152195yba; Tue, 14 May 2019 02:37:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqwW520v1wyUMB30t3dnJNVJnSimj58RZrw0zIwFvEEoX68pPQtb/6Av2hmqAKGkl2tLs+4S X-Received: by 2002:aa7:9577:: with SMTP id x23mr39432207pfq.164.1557826669552; Tue, 14 May 2019 02:37:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557826669; cv=none; d=google.com; s=arc-20160816; b=zExo/lQsNVG3XttDwwDHvONGudYfaXsKJc3ivAwpkp5VCw04FMyWPH1DB9ol5bLq9S QNEUFY1AWTLZ/UlOLzhWHzeK34Rj8KrV1gQjTnQjquZ9EY5lyl38rPQvDCFfygBk7iWc Bc6H+2MuC4tcX+edhSKTzPdwMfwBYjovSM9ISWGEmvNmA4LEnG6FBlGLp+LQ5+4KId9h dYCtv5zxCBYSpl38fkGle0dJZ5VKq3s8S3lfSOCbFaDHFIxxfKolCOtamMU5e1mYYnsd 6i/HJQJu/M1mnxMNcZoxz3/Ui2jwdThTffwEcKbETuRlGe//thmLHk7nselWePfIUR76 2vIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LzYSQmTyf5/EQ3Y2VGObHjM41SSi7kcFjXdBikk9ZQs=; b=bl6+METwuVClcO2fSvVM61Rt42gAy+AP5Czp4yr2BU6/9fxDNxIekXN+su3phtVsWM jrGnycr/2g6xVj69WgD1SG8WtBzd3r24nDE4dtOKLx3XwZMpDEmkEXyQJGn3RZl9CsdM 0ErJN+J0YgFFfFvLMjIEkS3co7d7UR+bUyMsgekMFH3/mx37d57FF+yx1/mFBGt97SIZ 6/wVqVjaKbsVDrXMd8v44sCtNx7Fr4btgXcw/6t8CGojVq0A3sETzgz0N9Qto68HbDKo y3DuoAW3qyBKrFlAGZV4WKZwyPgyj5dxvVRKto5CdhnNbR9ELkMzXDqgKa87kq74kLad EQMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=vx3HrLuh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g191si20015130pgc.197.2019.05.14.02.37.34; Tue, 14 May 2019 02:37:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=vx3HrLuh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726441AbfENJgY (ORCPT + 99 others); Tue, 14 May 2019 05:36:24 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:14074 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725916AbfENJgX (ORCPT ); Tue, 14 May 2019 05:36:23 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4E9W0r5031412; Tue, 14 May 2019 11:36:12 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=STMicroelectronics; bh=LzYSQmTyf5/EQ3Y2VGObHjM41SSi7kcFjXdBikk9ZQs=; b=vx3HrLuhnX85QMXeDgz/T1DXa6z04dnJ2EKrOm4UEz4vgiJab7dGEgdv0Lgva2qmXbGX 3c0i9waUV0OHFrsgZfXK8Kr6wx38f0DMwHJAUAmYkRbrxVXiR34HPhJ3u9c89EzZFaT3 x7Y3j4+RsVnXXVM7bC7TXwPqz1JWCdBdDYcX/MK0tKLnfAOvScT3hnLVhku40mJyT3Jy KgtmhZDIeDpAbJIzrZaJ8orwmfUHl7/cbqvQj3ZMdeTFPPSzMBbg4ugScy7OPfmi2dLz x8sumPvk/YOvVolGRWbOO6WEq8ehoBwotVQli88hxSaSy7yNViUppqPQqsvaIbTQ37Pq Cg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2sek5aa5dp-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 14 May 2019 11:36:12 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AB19534; Tue, 14 May 2019 09:36:11 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 82D58179A; Tue, 14 May 2019 09:36:11 +0000 (GMT) Received: from SAFEX1HUBCAS24.st.com (10.75.90.95) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 14 May 2019 11:36:11 +0200 Received: from localhost (10.201.23.97) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 14 May 2019 11:36:10 +0200 From: =?UTF-8?q?Yannick=20Fertr=C3=A9?= To: Yannick Fertre , Philippe Cornu , Benjamin Gaignard , Vincent Abriou , David Airlie , Daniel Vetter , Maxime Coquelin , Alexandre Torgue , , , , Subject: [PATCH v4 1/2] dt-bindings: display: stm32: add supply property to DSI controller Date: Tue, 14 May 2019 11:35:55 +0200 Message-ID: <1557826556-10079-2-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557826556-10079-1-git-send-email-yannick.fertre@st.com> References: <1557826556-10079-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-05-14_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds documentation of a new property phy-dsi-supply to the STM32 DSI controller. Signed-off-by: Yannick Fertré Reviewed-by: Rob Herring Reviewed-by: Philippe Cornu --- Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt index 3eb1b48..60c54da 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt @@ -40,6 +40,8 @@ Mandatory nodes specific to STM32 DSI: - panel or bridge node: A node containing the panel or bridge description as documented in [6]. - port: panel or bridge port node, connected to the DSI output port (port@1). +Optional properties: +- phy-dsi-supply: phandle of the regulator that provides the supply voltage. Note: You can find more documentation in the following references [1] Documentation/devicetree/bindings/clock/clock-bindings.txt @@ -101,6 +103,7 @@ Example 2: DSI panel clock-names = "pclk", "ref"; resets = <&rcc STM32F4_APB2_RESET(DSI)>; reset-names = "apb"; + phy-dsi-supply = <®18>; ports { #address-cells = <1>; -- 2.7.4