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[209.85.167.54]) by smtp.gmail.com with ESMTPSA id b23sm3879828lfg.41.2019.05.14.09.18.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 09:18:41 -0700 (PDT) Received: by mail-lf1-f54.google.com with SMTP id y19so12355608lfy.5 for ; Tue, 14 May 2019 09:18:41 -0700 (PDT) X-Received: by 2002:ac2:5a41:: with SMTP id r1mr17174747lfn.148.1557850250052; Tue, 14 May 2019 09:10:50 -0700 (PDT) MIME-Version: 1.0 References: <20190424123656.484227701@infradead.org> <20190424124421.636767843@infradead.org> <20190424211759.52xraajqwudc2fza@pburton-laptop> <2b2b07cc.bf42.16a52dc4e4d.Coremail.huangpei@loongson.cn> <20190425073348.GV11158@hirez.programming.kicks-ass.net> <20190425091258.GC14281@hirez.programming.kicks-ass.net> <20190514155813.GG2677@hirez.programming.kicks-ass.net> In-Reply-To: <20190514155813.GG2677@hirez.programming.kicks-ass.net> From: Linus Torvalds Date: Tue, 14 May 2019 09:10:34 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: Re: [RFC][PATCH 2/5] mips/atomic: Fix loongson_llsc_mb() wreckage To: Peter Zijlstra Cc: huangpei@loongson.cn, Paul Burton , "stern@rowland.harvard.edu" , "akiyks@gmail.com" , "andrea.parri@amarulasolutions.com" , "boqun.feng@gmail.com" , "dlustig@nvidia.com" , "dhowells@redhat.com" , "j.alglave@ucl.ac.uk" , "luc.maranget@inria.fr" , "npiggin@gmail.com" , "paulmck@linux.ibm.com" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , Huacai Chen Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 14, 2019 at 8:58 AM Peter Zijlstra wrote: > > So if two variables share a line, and one is local while the other is > shared atomic, can contention on the line, but not the variable, cause > issues for the local variable? > > If not; why not? Because so far the issue is line granular due to the > coherence aspect. If I understood the issue correctly, it's not that cache coherence doesn't work, it's literally that the sc succeeds when it shouldn't. In other words, it's not going to affect anything else, but it means that "ll/sc" isn't actually truly atomic, because the cacheline could have bounced around to another CPU in the meantime. So we *think* we got an atomic update, but didn't, and the "ll/sc" pair ends up incorrectly working as a regular "load -> store" pair, because the "sc' incorrectly thought it still had exclusive access to the line from the "ll". The added memory barrier isn't because it's a memory barrier, it's just keeping the subsequent speculative instructions from getting the cacheline back and causing that "sc" confusion. But note how from a cache coherency standpoint, it's not about the cache coherency being wrong, it's literally just about the ll/sc not giving the atomicity guarantees that the sequence is *supposed* to give. So an "atomic_inc()" can basically (under just the wrong circumstances) essentially turn into just a non-atomic "*p++". NOTE! I have no actual inside knowledge of what is going on. The above is purely my reading of this thread, and maybe I have mis-understood. Linus