Received: by 2002:a25:4158:0:0:0:0:0 with SMTP id o85csp338046yba; Thu, 16 May 2019 01:28:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqxV0Xov6/aUg3PTWb/ag38H10+gpgtSX8rd/u+go8HYRNPUyqZBnlfLf+tHbm0j5L3PXA3y X-Received: by 2002:a17:902:b703:: with SMTP id d3mr47333738pls.93.1557995283217; Thu, 16 May 2019 01:28:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557995283; cv=none; d=google.com; s=arc-20160816; b=M7WAvBpq529ZMcleUskYnfoY0RYARJQcdqTSTaDUcp6C0eO6g3ZkVNz+zX+KA1l3Tp rHAu+lDBnUCwcYXq5SeApAHAUusHThi1IpjQ8VwmHMTmh5vM3Lc+HYJ1gftcqtIGV1Sr ErVEqPNBqlg/VY4vBCTR2+27+atIyYxBa9V7gWxXBx3m1W8xl+u7xS8G5YoxE12zuAh8 KiQ1tuCEF5ps+MzPkDRAkeoPtxYnNekC77KfSkXoTqBqZLoNwRELFGj6oEY65moLYZWL VYcJGIdh1yCfljjGLPEZ2VnBImcPTIb7d8TlU1gJeUyHzQ3QYvuUaJ0wZnQ1GgDbblys eLwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=sNifsM3fduVIDSZycbI3ENhjtnEvwJmE3NYKouG5gyY=; b=V7KIb02q8hqlLpVeZEdtW+zbIc+rMfO5TYD6dQm/rkWLEOh+FAVt5o+ACvi04wSHz2 ICPvSdGjawJcQyaSGReG5iT1IVa7ZYYF3tIk3BXIbDEN75K02eAhEKY6h6IJ92txH6RS hfq/VkElufHM+Lzo5nvojYegqi6ErbrLbmOfXcgZCG5XxTZFKiIuGWfO2da1FwQzSu9e 9aWHn8OWV+5dCAVPWrcuNGdN8i+OYrePvKvooY2PJJmP8HJHmNMpujBsWxKdS6RgiBZW pk+yi1cTRRa5ghseMUMpNXYkQy/gkJedMHzg/NyZVEYTM92wlFVv9zyVYnJ+KXG2fHSI +W8Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 35si2143063plb.228.2019.05.16.01.27.48; Thu, 16 May 2019 01:28:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726279AbfEPI0l (ORCPT + 99 others); Thu, 16 May 2019 04:26:41 -0400 Received: from mga11.intel.com ([192.55.52.93]:22098 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726748AbfEPI0k (ORCPT ); Thu, 16 May 2019 04:26:40 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 May 2019 01:26:40 -0700 X-ExtLoop1: 1 Received: from skl-s2.bj.intel.com ([10.240.192.102]) by orsmga005.jf.intel.com with ESMTP; 16 May 2019 01:26:38 -0700 From: Luwei Kang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com, Luwei Kang Subject: [PATCH v1 1/6] x86/fpu: Introduce new fpu state for Intel processor trace Date: Thu, 16 May 2019 16:25:09 +0800 Message-Id: <1557995114-21629-2-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1557995114-21629-1-git-send-email-luwei.kang@intel.com> References: <1557995114-21629-1-git-send-email-luwei.kang@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce new fpu state structure pt_state to save Intel processor trace configuration. The upcoming using XSAVES/XRSTORS to switch the Intel PT configuration on VM-Entry/Exit will use this structure. Signed-off-by: Luwei Kang --- arch/x86/include/asm/fpu/types.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/types.h index 2e32e17..8cbb42e 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -221,6 +221,19 @@ struct avx_512_hi16_state { } __packed; /* + * State component 8 is used for some 64-bit registers + * of Intel processor trace. + */ +struct pt_state { + u64 rtit_ctl; + u64 rtit_output_base; + u64 rtit_output_mask; + u64 rtit_status; + u64 rtit_cr3_match; + u64 rtit_addrx_ab[0]; +} __packed; + +/* * State component 9: 32-bit PKRU register. The state is * 8 bytes long but only 4 bytes is used currently. */ -- 1.8.3.1