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From:   "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To:     "Luck, Tony" <tony.luck@intel.com>
CC:     "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "bp@suse.de" <bp@suse.de>, "x86@kernel.org" <x86@kernel.org>
Subject: RE: [PATCH v3 5/6] x86/MCE: Save MCA control bits that get set in
 hardware
Thread-Topic: [PATCH v3 5/6] x86/MCE: Save MCA control bits that get set in
 hardware
Thread-Index: AQHU/5PPbonhoiIaT0+tpMBUt0fOpKZt/3MAgAAEtbA=
Date:   Thu, 16 May 2019 16:14:14 +0000
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References: <20190430203206.104163-1-Yazen.Ghannam@amd.com>
 <20190430203206.104163-6-Yazen.Ghannam@amd.com>
 <20190516155202.GA11517@agluck-desk>
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> -----Original Message-----
> From: Luck, Tony <tony.luck@intel.com>
> Sent: Thursday, May 16, 2019 10:52 AM
> To: Ghannam, Yazen <Yazen.Ghannam@amd.com>
> Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; bp@suse.de;=
 x86@kernel.org
> Subject: Re: [PATCH v3 5/6] x86/MCE: Save MCA control bits that get set i=
n hardware
>=20
>=20
> On Tue, Apr 30, 2019 at 08:32:20PM +0000, Ghannam, Yazen wrote:
> > diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/c=
ore.c
> > index 986de830f26e..551366c155ef 100644
> > --- a/arch/x86/kernel/cpu/mce/core.c
> > +++ b/arch/x86/kernel/cpu/mce/core.c
> > @@ -1567,10 +1567,13 @@ static void __mcheck_cpu_init_clear_banks(void)
> >       for (i =3D 0; i < this_cpu_read(mce_num_banks); i++) {
> >               struct mce_bank *b =3D &mce_banks[i];
> >
> > -             if (!b->init)
> > -                     continue;
> > -             wrmsrl(msr_ops.ctl(i), b->ctl);
> > -             wrmsrl(msr_ops.status(i), 0);
> > +             if (b->init) {
> > +                     wrmsrl(msr_ops.ctl(i), b->ctl);
> > +                     wrmsrl(msr_ops.status(i), 0);
> > +             }
> > +
> > +             /* Save bits set in hardware. */
> > +             rdmsrl(msr_ops.ctl(i), b->ctl);
> >       }
> >  }
>=20
> This looks like it will be a problem for Intel CPUs. If
> we take a CPU offline, and then bring it back again, we
> ues "b->ctl" to reinitialize the register in mce_reenable_cpu().
>=20
> But Intel SDM says at the end of section "15.3.2.1 IA32_MCi_CTL_MSRs"
>=20
>         "P6 family processors only allow the writing of all 1s or all
>         0s to the IA32_MCi_CTL MSR."
>=20

I can put a vendor check on the read. Is that sufficient?

Thanks,
Yazen