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[209.85.217.54]) by smtp.gmail.com with ESMTPSA id 143sm4199125vkj.44.2019.05.16.14.47.22 for (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Thu, 16 May 2019 14:47:22 -0700 (PDT) Received: by mail-vs1-f54.google.com with SMTP id q64so3324974vsd.1 for ; Thu, 16 May 2019 14:47:22 -0700 (PDT) X-Received: by 2002:a67:dd8e:: with SMTP id i14mr18643024vsk.149.1558042747509; Thu, 16 May 2019 14:39:07 -0700 (PDT) MIME-Version: 1.0 References: <5cdae78b.1c69fb81.a32a9.870f@mx.google.com> In-Reply-To: <5cdae78b.1c69fb81.a32a9.870f@mx.google.com> From: Doug Anderson Date: Thu, 16 May 2019 14:38:52 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: next/master boot bisection: next-20190514 on rk3288-veyron-jaq To: "kernelci.org bot" Cc: Tomeu Vizoso , Guillaume Tucker , mgalka@collabora.com, Mark Brown , matthew.hart@linaro.org, Kevin Hilman , Enric Balletbo i Serra , Elaine Zhang , Eduardo Valentin , Daniel Lezcano , Heiko Stuebner , Linux PM , LKML , "open list:ARM/Rockchip SoC..." , Zhang Rui , Linux ARM , Matthias Kaehlcke Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, From: kernelci.org bot Date: Tue, May 14, 2019 at 9:06 AM To: , , , , , , , Elaine Zhang, Eduardo Valentin, Daniel Lezcano Cc: Heiko Stuebner, , , , Zhang Rui, > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * > * This automated bisection report was sent to you on the basis * > * that you may be involved with the breaking commit it has * > * found. No manual investigation has been done to verify it, * > * and the root cause of the problem may be somewhere else. * > * Hope this helps! * > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * > > next/master boot bisection: next-20190514 on rk3288-veyron-jaq > > Summary: > Start: 0a13f187b16a Add linux-next specific files for 20190514 > Details: https://kernelci.org/boot/id/5cda7f2259b514876d7a3628 > Plain log: https://storage.kernelci.org//next/master/next-20190514/arm/multi_v7_defconfig+CONFIG_EFI=y+CONFIG_ARM_LPAE=y/gcc-8/lab-collabora/boot-rk3288-veyron-jaq.txt > HTML log: https://storage.kernelci.org//next/master/next-20190514/arm/multi_v7_defconfig+CONFIG_EFI=y+CONFIG_ARM_LPAE=y/gcc-8/lab-collabora/boot-rk3288-veyron-jaq.html > Result: 691d4947face thermal: rockchip: fix up the tsadc pinctrl setting error > > Checks: > revert: PASS > verify: PASS > > Parameters: > Tree: next > URL: git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git > Branch: master > Target: rk3288-veyron-jaq > CPU arch: arm > Lab: lab-collabora > Compiler: gcc-8 > Config: multi_v7_defconfig+CONFIG_EFI=y+CONFIG_ARM_LPAE=y > Test suite: boot > > Breaking commit found: > > ------------------------------------------------------------------------------- > commit 691d4947faceb8bd841900049e07c81c95ca4b0d > Author: Elaine Zhang > Date: Tue Apr 30 18:09:44 2019 +0800 > > thermal: rockchip: fix up the tsadc pinctrl setting error > > Explicitly use the pinctrl to set/unset the right mode > instead of relying on the pinctrl init mode. > And it requires setting the tshut polarity before select pinctrl. > > When the temperature sensor mode is set to 0, it will automatically > reset the board via the Clock-Reset-Unit (CRU) if the over temperature > threshold is reached. However, when the pinctrl initializes, it does a > transition to "otp_out" which may lead the SoC restart all the time. > > "otp_out" IO may be connected to the RESET circuit on the hardware. > If the IO is in the wrong state, it will trigger RESET. > (similar to the effect of pressing the RESET button) > which will cause the soc to restart all the time. > > Signed-off-by: Elaine Zhang > Reviewed-by: Daniel Lezcano > Signed-off-by: Eduardo Valentin I can confirm that the above commit breaks my jerry, though I haven't dug into the details. :( Is anyone fixing? For now I'm just booting with the revert. -Doug