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Date:   Fri, 17 May 2019 18:37:29 +0200
From:   Borislav Petkov <bp@alien8.de>
To:     "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
Cc:     "Luck, Tony" <tony.luck@intel.com>,
        "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH v3 5/6] x86/MCE: Save MCA control bits that get set in
 hardware
Message-ID: <20190517163729.GE13482@zn.tnic>
References: <20190516155202.GA11517@agluck-desk>
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On Fri, May 17, 2019 at 03:46:07PM +0000, Ghannam, Yazen wrote:
> I think there are a couple of issues here.
> 1) The bank is being initialized without accounting for any quirks.

Almost. __mcheck_cpu_init_clear_banks() a little bit later corrects
that. I guess I can drop the

	wrmsrl(msr_ops.status(i), 0);

in here because __mcheck_cpu_init_clear_banks() does that too.

Now, the

	wrmsrl(msr_ops.ctl(i), -1)
	rdmsrl(msr_ops.ctl(i), val);

method of throwing all 1s to see what sticks is what Intel wants, as
Tony said. Is that going to be a problem on AMD?

> 2) The bank is being initialized without having set up any handler or
> other appropriate setup.

I'm afraid you're going to have to explain this in more detail...

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.