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[209.132.180.67]) by mx.google.com with ESMTP id b12si21526561pge.261.2019.05.21.02.38.32; Tue, 21 May 2019 02:38:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AIHFm7Hp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727791AbfEUJf7 (ORCPT + 99 others); Tue, 21 May 2019 05:35:59 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:33043 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727779AbfEUJf5 (ORCPT ); Tue, 21 May 2019 05:35:57 -0400 Received: by mail-pg1-f196.google.com with SMTP id h17so8318966pgv.0 for ; Tue, 21 May 2019 02:35:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=dTr1UCKgplI1VGB/ZytO9oL3rPosZf7DuDvgJME+3jg=; b=AIHFm7Hp4l+4xNPyW1cX8dxq1awTwXVWdpBPVIR3sn4SXcSKSHlVgGImRIW5bXDUa4 lo0tOlSuFOBUL1R3fbgd7cJUHoMk3my3qscAJTjjlf/AViZ3Vv/IgzxGSayFt4cE7Uu2 0yWa5KvdgnE3+HdLj8ccnl1VQk3XVLm0yogjlk4FzbxrTC6hy9u35nLQCSB1cl/ytpsd AyPweRXFYA029GowWgM4Ql7lqa32mdbC2QzGMEhwG3atEB8r1k6aNOXYlrFd2IWMEY7F yCU6/Fy2CcxuhHznLygRhUT09LrZukpgH9Ftt7fSNGiz7zcuSZqAYVm6a2dVYdDQE1Lf s2UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=dTr1UCKgplI1VGB/ZytO9oL3rPosZf7DuDvgJME+3jg=; b=GLhlmhCjIvz4/5kxABjNiM6vDK4Z4vYamaAjjEsqs9kAl31gVi7v0LL7J/vRh0/3ks kGgRFOrnYJoP/KR0+aVo/SkyhoGGVkD/AcBG24o+Lmg4qraGcB56BSc518Dp3BHfEPev MPvUhQ9kDXEnzlhelHUNcIU/4b5XhazPH7WRKfXVZR3bfHj8bY1uZ7iOILkg5kd9yEFJ zvcWSlW1P8zy7dHzc5SFCdzeKyPKEDthLCwArhsGP5VvhpkHUFyeFiSjaUSD7D+muPR1 zijDmSskreAD4WX2QG2QJ/x5WraUxqESAle0kz/KVt6Dz8DL07WjCyPuy6mFNa0L3Vwu Tz4w== X-Gm-Message-State: APjAAAUoh2icCa/837sNmGEkDLnH8SbsXujipOKs2Z+XrXP+nW6w1MRT bRD5qIpbE+7Yyzk0yQXT5VVKyanHt90BiQ== X-Received: by 2002:a63:4c06:: with SMTP id z6mr80149345pga.296.1558431356498; Tue, 21 May 2019 02:35:56 -0700 (PDT) Received: from localhost ([49.248.189.249]) by smtp.gmail.com with ESMTPSA id q20sm22215653pgq.66.2019.05.21.02.35.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 May 2019 02:35:55 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo Cc: devicetree@vger.kernel.org Subject: [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus Date: Tue, 21 May 2019 15:05:19 +0530 Message-Id: <5224535a7ef5b257e3baa698991bf6deeefccc36.1558430617.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement the same microarchitecture and the two clusters only differ in the maximum frequency attainable by the CPUs. Add capacity-dmips-mhz property to allow the topology code to determine the actual capacity by taking into account the highest frequency for each CPU. Signed-off-by: Amit Kucheria Suggested-by: Daniel Lezcano --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4f2fb7885f39..e0e8f30ce11a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -96,6 +96,7 @@ reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -109,6 +110,7 @@ reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; }; @@ -118,6 +120,7 @@ reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -131,6 +134,7 @@ reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; }; -- 2.17.1