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[78.210.255.2]) by smtp.googlemail.com with ESMTPSA id 74sm3013102wma.7.2019.05.21.05.20.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 May 2019 05:20:25 -0700 (PDT) Subject: Re: [PATCH v4 2/2] driver: clocksource: Add nxp system counter timer driver support To: Jacky Bai , "tglx@linutronix.de" , "robh+dt@kernel.org" , "shawnguo@kernel.org" , "mark.rutland@arm.com" , Aisheng Dong Cc: "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , dl-linux-imx References: <20190521072355.12928-1-ping.bai@nxp.com> <20190521072355.12928-2-ping.bai@nxp.com> <5823cd07-312b-600c-1b78-dc5bff2a12eb@linaro.org> From: Daniel Lezcano Message-ID: Date: Tue, 21 May 2019 14:20:15 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/05/2019 14:01, Jacky Bai wrote: > >> -----Original Message----- >> From: Daniel Lezcano [mailto:daniel.lezcano@linaro.org] >> Sent: Tuesday, May 21, 2019 6:08 PM >> To: Jacky Bai ; tglx@linutronix.de; robh+dt@kernel.org; >> shawnguo@kernel.org; mark.rutland@arm.com; Aisheng Dong >> >> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; dl-linux-imx >> >> Subject: Re: [PATCH v4 2/2] driver: clocksource: Add nxp system counter timer >> driver support >> >> On 21/05/2019 09:18, Jacky Bai wrote: >>> From: Bai Ping >>> >>> The system counter (sys_ctr) is a programmable system counter which >>> provides a shared time base to the Cortex A15, A7, A53 etc cores. >>> It is intended for use in applications where the counter is always >>> powered on and supports multiple, unrelated clocks. The sys_ctr >>> hardware >>> supports: >>> - 56-bit counter width (roll-over time greater than 40 years) >> >> The benefit of using more than 32bits on a 32bits system is not proven. >> > > It is mainly used on 64bit ARMv8 system. Oh, ok. Fair enough. > >> The function to read and build the 56bits value can have a very significant >> impact on the performance of your platform. >> >> Using a 32bits counter can be enough if it does not wrap too fast. >> >> Can you consider a 32 bits counter ? > > this counter is ARMv8 arch timer's counter source. As it also has timer function, so I choose it > to act as a broadcast timer for cpuidle. The timer interrupt can only be triggered when 'compare[55:0] <= counter[55:0]'. > So you mean that only use the lower 32bit to implement this timer? If so, I can change to use only the lower 32bit. IMO it is preferable but you decide (probably compare with how long it takes to wrap when 32bits). -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog