Received: by 2002:a25:86ce:0:0:0:0:0 with SMTP id y14csp1584528ybm; Thu, 23 May 2019 03:36:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqxDbYuG9A/95uORPEhrEN351Ts/cFRutduX5st4/XXFTMpb/GO3VqZ2Z7HyMx9I1WTofBcn X-Received: by 2002:a65:430a:: with SMTP id j10mr50474089pgq.133.1558607815959; Thu, 23 May 2019 03:36:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558607815; cv=none; d=google.com; s=arc-20160816; b=bX5usp/vzFtgC93BRWYqUGMBh2PFTGlhLlDypeKkllbUgNp+WgzeNGIazY1njFb1Lj iHKxnnOgIO9NKhZn/1T/ylW0sjCxuCyr831jcVZXzBJaBAhOqq6e9yPtRyHI4mAH6/UZ cKnsRlLYqwIzfKRy99PcXt/rhpARf/gRtscbcWYhKHmkR8bvwaOcQzBFwkcly+2LRACt 7iWG0Ag6MNDOyACBf4jH1mc3QnlTNPmX05SVMc90V9pO/bZ3FhyFxDTxopgkqsZwhgxs zZENF7YxpSRduzpQ1wR0RvFwESH5eCbE0MjmKsWSz0hRZMvyVRVfaKcwctpeQzHMu8rq Vz8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=ExlK6PnLDhu2IuxuGJTRM/BmCvUZtacJPYgujt4keDs=; b=qPSopMbxta1LVAN0PSj2FAp++itk1xdSF5P1x91pPnkToQIZ6igVxB9VLu/EeHiOvi sQmZoeZilrCYuxEVrKON8/bexOlVHsOas8eBhjxaGbwgLsdHICbEDZIxDs7TBlHklJsg bTq6c1EL6pHHRfNuegaw7Qvk/MEmOF1+rXM+rZxQSBAIx8fEBObi/bg66BBFhmPWw18+ 92zF3QkREPqo83V4KfxZGMJOFpvQ822X+eij/XgcKs69UBtc6qvkPJdo+ltwssdFr+CA CeVQaeAeW0jfB9uWFh/GCRpgwWV/FT6skrQYHlyak04sqFNX4IgLhYQyhWSxSOpz+11f Ef7Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b12si30194668pge.261.2019.05.23.03.36.39; Thu, 23 May 2019 03:36:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730453AbfEWKf0 (ORCPT + 99 others); Thu, 23 May 2019 06:35:26 -0400 Received: from foss.arm.com ([217.140.101.70]:43018 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730381AbfEWKf0 (ORCPT ); Thu, 23 May 2019 06:35:26 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D9B9341; Thu, 23 May 2019 03:35:25 -0700 (PDT) Received: from usa.arm.com (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7F6473F718; Thu, 23 May 2019 03:35:23 -0700 (PDT) From: Sudeep Holla To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Cc: Sudeep Holla , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Christoffer Dall , Marc Zyngier , James Morse , Suzuki K Pouloze , Catalin Marinas , Will Deacon , Julien Thierry Subject: [PATCH v2 02/15] dt-bindings: ARM SPE: highlight the need for PPI partitions on heterogeneous systems Date: Thu, 23 May 2019 11:34:49 +0100 Message-Id: <20190523103502.25925-3-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190523103502.25925-1-sudeep.holla@arm.com> References: <20190523103502.25925-1-sudeep.holla@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It's not entirely clear for the binding document that the only way to express ARM SPE affined to a subset of CPUs on a heterogeneous systems is through the use of PPI partitions available in the interrupt controller bindings. Let's make it clear. Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/spe-pmu.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt b/Documentation/devicetree/bindings/arm/spe-pmu.txt index 93372f2a7df9..4f4815800f6e 100644 --- a/Documentation/devicetree/bindings/arm/spe-pmu.txt +++ b/Documentation/devicetree/bindings/arm/spe-pmu.txt @@ -9,8 +9,9 @@ performance sample data using an in-memory trace buffer. "arm,statistical-profiling-extension-v1" - interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where - SPE is only supported on a subset of the CPUs, please consult - the arm,gic-v3 binding for details on describing a PPI partition. + SPE is only supported on a subset of the CPUs, a PPI partition + described in the arm,gic-v3 binding must be used to describe + the set of CPUs this interrupt is affine to. ** Example: -- 2.17.1