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[209.85.217.42]) by smtp.gmail.com with ESMTPSA id p7sm4642485vsp.34.2019.05.23.08.13.11 for (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 08:13:26 -0700 (PDT) Received: by mail-vs1-f42.google.com with SMTP id z11so3798308vsq.9 for ; Thu, 23 May 2019 08:13:11 -0700 (PDT) X-Received: by 2002:a67:ebd6:: with SMTP id y22mr31596912vso.87.1558624390840; Thu, 23 May 2019 08:13:10 -0700 (PDT) MIME-Version: 1.0 References: <20190501043734.26706-1-bjorn.andersson@linaro.org> <20190501043734.26706-4-bjorn.andersson@linaro.org> In-Reply-To: <20190501043734.26706-4-bjorn.andersson@linaro.org> From: Doug Anderson Date: Thu, 23 May 2019 08:12:56 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v7 3/4] arm64: dts: qcom: Add AOSS QMP node To: Bjorn Andersson Cc: Andy Gross , David Brown , Rob Herring , Mark Rutland , Stephen Boyd , linux-arm-msm , devicetree@vger.kernel.org, LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Tue, Apr 30, 2019 at 9:37 PM Bjorn Andersson wrote: > > The AOSS QMP provides a number of power domains, used for QDSS and > PIL, add the node for this. > > Tested-by: Sibi Sankar > Reviewed-by: Sibi Sankar > Signed-off-by: Bjorn Andersson > --- > > Changes since v6: > - Added #clock-cells > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index fcb93300ca62..666bc88d3e81 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -2142,6 +2143,15 @@ Please avoid editing patches by hand. I needed to manually change the "15" above to "16" to apply. -Doug