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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: ec2f4537-2761-43cc-1b08-08d6dfa754b8 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 May 2019 17:51:49.1715 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lewan@microsoft.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR21MB1191 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org (+Rui/Hang/Sasha) Hi Mark, please see inline with "[Lei]" tag. Thanks! -Lei -----Original Message----- From: Mark Rutland =20 Sent: Thursday, May 23, 2019 9:59 AM To: Lei Wang Cc: bp@alien8.de; james.morse@arm.com; robh+dt@kernel.org; devicetree@vger.= kernel.org; linux-kernel@vger.kernel.org; linux-edac@vger.kernel.org; Lei W= ang (BSP) Subject: Re: [PATCH v3 1/2] dt-bindings: edac: arm-dmc520.txt On Thu, May 16, 2019 at 02:35:47AM +0000, Lei Wang wrote: > From: Lei Wang >=20 > This is the device tree bindings for new EDAC driver dmc520_edac.c. >=20 > Signed-off-by: Lei Wang > --- > .../devicetree/bindings/edac/arm-dmc520.txt | 26 ++++++++++++++++= ++++++ > 1 file changed, 26 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/arm-dmc520.txt >=20 > diff --git a/Documentation/devicetree/bindings/edac/arm-dmc520.txt b/Docu= mentation/devicetree/bindings/edac/arm-dmc520.txt > new file mode 100644 > index 0000000..71e7aa3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/arm-dmc520.txt > @@ -0,0 +1,26 @@ > +* ARM DMC-520 EDAC node > + > +Required properties: > +- compatible : "brcm,dmc-520", "arm,dmc-520". > +- reg : Address range of the DMC-520 registers. > +- interrupts : DMC-520 interrupt numbers. The example below specifies > + two interrupt lines for dram_ecc_errc_int and > + dram_ecc_errd_int. > +- interrupt-config : This is an array of interrupt masks. For each of th= e > + above interrupt line, add one interrupt mask element to > + it. That is, there is a 1:1 mapping from each interrupt > + line to an interrupt mask. An interrupt mask can represent > + multiple interrupts being enabled. Refer to interrupt_control > + register in DMC-520 TRM for interrupt mapping. In the example > + below, the interrupt configuration enables dram_ecc_errc_int > + and dram_ecc_errd_int. And each interrupt is connected to > + a separate interrupt line. Generally we use interrupt-names to distinguish interrupts. Do you really have arbitary subsets of lines muxed together? ----------------------------------------------- [Lei] Yes it is possible to mux multiple interrupt sources into one interru= pt line for dmc520. For example, in this particular brcm implementation,=20 Line 841: source dram_ecc_errc_int Line 843: source dram_ecc_errd_int Line 839: source dram_ecc_errc_int and dram_ecc_errd_int There are two possibilities for implementing ecc counts for ce/ue. And we c= hose to use the single source line. But it's possible to implement using th= e combined-source line too. This dt binding can support both by modifying t= he properties. ------------------------------------------------- Thanks, Mark. > + > +Example: > + > +dmc0: dmc@200000 { > + compatible =3D "brcm,dmc-520", "arm,dmc-520"; > + reg =3D <0x200000 0x80000>; > + interrupts =3D <0x0 0x349 0x4>, <0x0 0x34B 0x4>; > + interrupt-config =3D <0x4>, <0x8>; > +}; > --=20 > 2.7.4 >=20