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[209.132.180.67]) by mx.google.com with ESMTP id 187si27318089pfe.116.2019.05.28.16.10.29; Tue, 28 May 2019 16:10:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=QONgxij4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727592AbfE1XJD (ORCPT + 99 others); Tue, 28 May 2019 19:09:03 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16479 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726653AbfE1XJC (ORCPT ); Tue, 28 May 2019 19:09:02 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 28 May 2019 16:08:59 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 28 May 2019 16:08:59 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 28 May 2019 16:08:59 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 28 May 2019 23:08:59 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 28 May 2019 23:08:59 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 28 May 2019 23:08:59 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.86]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 28 May 2019 16:08:58 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH V2 01/12] irqchip: tegra: do not disable COP IRQ during suspend Date: Tue, 28 May 2019 16:08:45 -0700 Message-ID: <1559084936-4610-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1559084936-4610-1-git-send-email-skomatineni@nvidia.com> References: <1559084936-4610-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1559084939; bh=gZyRtIANwX5Bl+mFYFbUEqD2HKsVf6EHmX45U++ZyJo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=QONgxij4Bt3SsjH0DI8ZOagMIx1eK0UwdB6S5/JuTl+epqAYCtfudpXZrJFizC8vS czd+TtKwgBi/DeEPp4YNGA41jWYWrKWlO5nkiHB9BhBdQGhiTcSw1y2B0edaTTGGD5 WMl+OY8yedtKD3vSyi+CutE16UAfxKxZdXXaPJA3pVObag4XVwcCi6NqBqYqjCxZq5 870b0rtSkcrO8N7JJeHCUJLM0rGEl21FisNGkJqROSesCXpmn40bukDudpafnAs7U5 4kKxEAnHk+NZNDFcu7/Yo/hKgDP1CoFFsQjCVgnvglGAsBVYrfbp7f7w+Vq9ixpOY1 j3QJY2DP/WySw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry sequence and sc7 entry firmware is run from COP/BPMP-Lite. So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence for Tegra210. This patch has fix for leaving the COP IRQ enabled for Tegra210 during interrupt controller suspend operation. Signed-off-by: Sowjanya Komatineni --- drivers/irqchip/irq-tegra.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c index 0abc0cd1c32e..deab3ba606e2 100644 --- a/drivers/irqchip/irq-tegra.c +++ b/drivers/irqchip/irq-tegra.c @@ -53,18 +53,22 @@ static unsigned int num_ictlrs; struct tegra_ictlr_soc { unsigned int num_ictlrs; + bool has_bpmp_fw; }; static const struct tegra_ictlr_soc tegra20_ictlr_soc = { .num_ictlrs = 4, + .has_bpmp_fw = false, }; static const struct tegra_ictlr_soc tegra30_ictlr_soc = { .num_ictlrs = 5, + .has_bpmp_fw = false, }; static const struct tegra_ictlr_soc tegra210_ictlr_soc = { .num_ictlrs = 6, + .has_bpmp_fw = true, }; static const struct of_device_id ictlr_matches[] = { @@ -76,6 +80,7 @@ static const struct of_device_id ictlr_matches[] = { struct tegra_ictlr_info { void __iomem *base[TEGRA_MAX_NUM_ICTLRS]; + struct tegra_ictlr_soc *soc; #ifdef CONFIG_PM_SLEEP u32 cop_ier[TEGRA_MAX_NUM_ICTLRS]; u32 cop_iep[TEGRA_MAX_NUM_ICTLRS]; @@ -156,8 +161,20 @@ static int tegra_ictlr_suspend(void) lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER); lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS); - /* Disable COP interrupts */ - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); + /* + * AVP/COP/BPMP-Lite is the Tegra boot processor. + * + * Tegra210 system suspend flow uses sc7entry firmware which + * is executed by COP/BPMP and it includes disabling COP IRQ, + * clamping CPU rail, turning off VDD_CPU, and preparing the + * system to go to LP0. + * + * COP/BPMP wakes up when COP IRQ is triggered and runs + * sc7entry-firmware. So need to keep COP interrupt enabled + * for Tegra210. + */ + if (!lic->soc->has_bpmp_fw) + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR); /* Disable CPU interrupts */ writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR); @@ -348,6 +365,7 @@ static int __init tegra_ictlr_init(struct device_node *node, goto out_unmap; } + lic->soc = soc; tegra_ictlr_syscore_init(); pr_info("%pOF: %d interrupts forwarded to %pOF\n", -- 2.7.4