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Date:   Wed, 29 May 2019 16:30:46 +0200
From:   Thierry Reding <thierry.reding@gmail.com>
To:     Sowjanya Komatineni <skomatineni@nvidia.com>
Cc:     jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net,
        marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch,
        mark.rutland@arm.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com,
        sboyd@kernel.org, linux-clk@vger.kernel.org,
        linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com,
        talho@nvidia.com, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org, mperttunen@nvidia.com,
        spatra@nvidia.com, robh+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH V2 08/12] soc/tegra: pmc: allow support for more tegra
 wake models
Message-ID: <20190529143046.GF17679@ulmo>
References: <1559084936-4610-1-git-send-email-skomatineni@nvidia.com>
 <1559084936-4610-9-git-send-email-skomatineni@nvidia.com>
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On Tue, May 28, 2019 at 04:08:52PM -0700, Sowjanya Komatineni wrote:
> This patch allows to create separate irq_set_wake and irq_set_type
> implementations for different tegra designs PMC that has different
> wake models which require difference wake registers and different
> programming sequence.
>=20
> AOWAKE model support is available for Tegra186 and Tegra194 only
> and it resides within PMC and supports tiered wake architecture.
>=20
> Tegra210 and prior tegra designs uses PMC directly to receive wake
> events and coordinate the wake sequence.
>=20
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
>  drivers/soc/tegra/pmc.c | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)
>=20
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index 5648e5c09ef5..974b4c9f6ada 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -235,6 +235,8 @@ struct tegra_pmc_soc {
>  	void (*setup_irq_polarity)(struct tegra_pmc *pmc,
>  				   struct device_node *np,
>  				   bool invert);
> +	int (*irq_set_wake)(struct irq_data *data, unsigned int on);
> +	int (*irq_set_type)(struct irq_data *data, unsigned int type);
> =20
>  	const char * const *reset_sources;
>  	unsigned int num_reset_sources;
> @@ -1915,12 +1917,15 @@ static const struct irq_domain_ops tegra_pmc_irq_=
domain_ops =3D {
>  	.alloc =3D tegra_pmc_irq_alloc,
>  };
> =20
> -static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
> +static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int=
 on)
>  {
>  	struct tegra_pmc *pmc =3D irq_data_get_irq_chip_data(data);
>  	unsigned int offset, bit;
>  	u32 value;
> =20
> +	if (data->hwirq =3D=3D ULONG_MAX)
> +		return 0;
> +
>  	offset =3D data->hwirq / 32;
>  	bit =3D data->hwirq % 32;
> =20

I've submitted this hunk as a separate patch because I think we may end
up needing to backport that to v5.0.

No need for you to worry about that, though. I'll take care of it when I
apply this patch.

Thierry

> @@ -1943,7 +1948,7 @@ static int tegra_pmc_irq_set_wake(struct irq_data *=
data, unsigned int on)
>  	return 0;
>  }
> =20
> -static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int ty=
pe)
> +static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int=
 type)
>  {
>  	struct tegra_pmc *pmc =3D irq_data_get_irq_chip_data(data);
>  	u32 value;
> @@ -1996,8 +2001,10 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pm=
c)
>  	pmc->irq.irq_unmask =3D irq_chip_unmask_parent;
>  	pmc->irq.irq_eoi =3D irq_chip_eoi_parent;
>  	pmc->irq.irq_set_affinity =3D irq_chip_set_affinity_parent;
> -	pmc->irq.irq_set_type =3D tegra_pmc_irq_set_type;
> -	pmc->irq.irq_set_wake =3D tegra_pmc_irq_set_wake;
> +	if (pmc->soc->irq_set_type)
> +		pmc->irq.irq_set_type =3D pmc->soc->irq_set_type;
> +	if (pmc->soc->irq_set_wake)
> +		pmc->irq.irq_set_wake =3D pmc->soc->irq_set_wake;
> =20
>  	pmc->domain =3D irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_no=
de,
>  					       &tegra_pmc_irq_domain_ops, pmc);
> @@ -2670,6 +2677,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc =
=3D {
>  	.regs =3D &tegra186_pmc_regs,
>  	.init =3D NULL,
>  	.setup_irq_polarity =3D tegra186_pmc_setup_irq_polarity,
> +	.irq_set_wake =3D tegra186_pmc_irq_set_wake,
> +	.irq_set_type =3D tegra186_pmc_irq_set_type,
>  	.reset_sources =3D tegra186_reset_sources,
>  	.num_reset_sources =3D ARRAY_SIZE(tegra186_reset_sources),
>  	.reset_levels =3D tegra186_reset_levels,
> @@ -2748,6 +2757,8 @@ static const struct tegra_pmc_soc tegra194_pmc_soc =
=3D {
>  	.regs =3D &tegra186_pmc_regs,
>  	.init =3D NULL,
>  	.setup_irq_polarity =3D tegra186_pmc_setup_irq_polarity,
> +	.irq_set_wake =3D tegra186_pmc_irq_set_wake,
> +	.irq_set_type =3D tegra186_pmc_irq_set_type,
>  	.num_wake_events =3D ARRAY_SIZE(tegra194_wake_events),
>  	.wake_events =3D tegra194_wake_events,
>  };
> --=20
> 2.7.4
>=20

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